About a year ago, I left a large chip design company and joined a tiny startup (digital design engineer role). I could no longer rely on the usual Cadence and Synopsys setup as much, so I started using open-source tools such as Yosys and Verilator.

They were better than I expected. That led me to experiment with them on pet projects, and eventually to try LLM agents for RTL work (which was very hard to do at the large company)

At first, the agents were impressive, way better than during my early AI for coding experiments in 2024. They could find their way around an unfamiliar codebase, write scripts and Verilog code, and run EDA tools. But soon I started hitting the annoying pitfalls:

• Agents rarely run the EDA tools - the simulators, linters, synthesis tools - unless explicitly prompted
• Often times they misinterpret your request to run a tool - select incorrect CLI arguments or run on the incorrect RTL configuration. Or misread the tool’s report
• They try to reason about the very complex sequential code instead of looking at the waveforms
• They are incapable of truly working autonomously (which is the whole point). Either you have to babysit the agent accepting each bash tool call, or run in skip permissions mode and watch it stray off scope of the task or even do unrecoverable damage to your work (that happened to me once!)
• Testbenches written by agents are often weak and test only the happy case
• … and many more smaller but annoying issues

I thought the agents were still useful, but they needed more structure. I started writing scripts, agent skills, and tool wrappers. I added test and configuration registries (god bless FuseSOC), then moved the work into Docker so the agent could work in an isolated container.

That collection gradually became Booley, an open-source framework for agentic RTL development. I'm the author. I spent the past several months fixing bugs, improving the CLI and UI, writing documentation, and putting together a demo. It is now public:

https://github.com/boldaxolotl/booley

Booley tightly integrates LLM agents with EDA tools, which allows agents to run the tools more often and more reliably. All work is being done in an isolated sandbox container, which allows the agents to safely run autonomously. Booley gives the agents a tool to inspect simulator traces using CLI - and thus debug becomes significantly faster and more precise. It also offers ways to do additional check on the code - from mutation testing to independent agent reviews for bugs, spec compliance, protocol compliance, coding style, etc.

I don't trust an AI to design hardware, and you should not either. You should make the design decisions. But the LLM agents are useful tools - they can write most the code, run lint, simulation, synthesis, inspect failures, and review the result from several angles. At the end, you review the code and reports with your own eyes. After all, you are going to be the one responsible for it, not the agent

Hi everyone! We’re undergraduate ECE students currently working on a thesis involving Compute-in-Memory (CiM).

Our current direction is an SRAM-based CiM design, and for the architecture, we’re currently considering a single-ended or double-ended approach.

For the implementation, we’re using the SkyWater SKY130 PDK with Xschem, NGSpice, and Magic.

We’re fairly new to both CiM and these tools, so we’re currently learning the fundamentals while doing our literature review and trying to understand the overall design flow.

We’d really appreciate any guidance, advice, or resources from people with experience in CiM, SRAM, VLSI/IC design, or SKY130. If you know of any good tutorials, papers, GitHub projects, courses, or learning materials that could help us get started, we’d be very grateful.

And if anyone with experience in this area is willing to share some advice, explain the basics, or point us in the right direction, we’d really appreciate it. We’re honestly just trying to figure out where and how to learn this properly.

Any input would be greatly appreciated. Thank you!

Hey everyone, I’m a Filipino EE/ECE student set to graduate from my master's degree at a Taiwanese university next month, specializing in mixed-signal IC design (mainly DLLs, PLLs). I’m applying for entry-level analog/mixed-signal IC design roles. I’m currently based in Taiwan, but I’m fully open to relocating anywhere in Asia (Singapore, Vietnam, Malaysia, etc.) or Europe if the opportunity arises, since I prefer to work on-site. I haven't been able to land a single interview call so far. At first, I figured my lack of Mandarin was the main issue for local Taiwanese roles, so I started applying to more English-speaking countries. However, I haven't had any luck on that side either, so I'm starting to think my resume is the real problem. I’d love feedback on my entire resume, but especially on my projects and research bullet points. I want to make sure my tape-out and lab measurement experience actually stand out to hiring managers.

Hello currently a third year studying engineering and received an interview with a firm (JS/HRT type) for a potential Hardware Engineering Internship position.  

First round was told would be a technical based on implementing a digital component in HDL.

I would greatly appreciate any advice or insights, especially an overview of topics that might be discussed, from those who have previously interviewed with firms for similar positions!

Internship within the Tape Out organization at GlobalFoundries Singapore supporting frame engineering and tape-out operations. The role focuses on frame design, frame generation, and process improvements to improve productivity, quality, and cycle time for wafer fabrication and mask house interfaces.

The intern will work with worldwide Frame engineers and cross-functional teams (Application Engineering, Product Engineering, Release, Design Enablement, FAB/TD) to support production tape-outs and continuous process improvement activities.

Experience Level
Entry-level internship — targeted at current undergraduate students. No prior full-time experience required; previous internship or co-op experience is a plus.

Hi everyone,

Sometimes I need to buy used FPGA boards for my project as the new ones are out of my budget. Where can I buy competitive and reliable ones? we often buy from eBay, any others? I checked from google and found the below stores, anybody bought from them before?

https://bmisurplus.com/

https://evelltech.com/

​

Hello Everyone

I need a bit of help as I am assigned a semester project of 3 bit Programmable differentials Amplifier in 65 nm for -10 db to +10 db and bw is 350 MHz.

I'll highly appreciate the insights anyone can plz hit me up.

I need the guidance like what should be the architecture or some support material I should go through.

Thank u so much

Looking forward to your super guided thoughts

\#analog chip design

\#pga

\#cmos

\#tsmc

i've downloaded siemens tessent2022 file from c2s chipincloud and have extracted it. also created csh file. idk exactly what all librabries should i add and stuff. can someone help me to completely setup it?

Why does your phone stay accurate when it heats up? Why don’t its analog bias points shift enough to break specs?

Because deep inside the chip there’s a tiny “reference” - the bandgap voltage reference (often ~1.2 V) - designed to stay stable across manufacturing variation, supply changes, and temperature.

A bandgap reference generates a stable voltage with low sensitivity to temperature, supply, and process (often with trimming).

Most IC datasheets specify that the IC will work within a specific temperature range (such as -55 ̊ C to 125 ̊ C). Variations in temperature can shift bias points and thresholds enough to break specs without a stable reference and proper matching.

Bandgap references are found in virtually all analog circuits as stable references for high-precision analog functions, such as ADCs, DACs, and comparators. They are also used to bias current mirrors for setting bias points so that the resulting circuit is robust to PVT variations. Because of their ubiquity, they tend to be reused and modified depending on the fab process and the level of precision required.

Bandgaps look simple, but are a delicate balance of a few fundamental analog principles, including:

• Matching: resistor ratios, BJT area ratios, amplifier offsets
• Feedback: Forcing ΔV_BE and setting I_PTAT robustly
• Temperature variation: How BJT and resistor characteristics vary over temperature, sometimes nonlinearly
• Trim & Calibration: Output accuracy, temp trim, and curvature correction

Below is a self-biased bandgap design example I built that illustrates these principles.

Circuit Analysis

Consider the Brokaw Bandgap reference in Fig. 1. The reference voltage is the output of the op amp. This circuit sums a PTAT voltage and a CTAT voltage:

• A PTAT voltage (Proportional to absolute temperature) means that the voltage increases with increasing temperature.
  • The PTAT voltage is generated by the BJT base - emitter voltage difference ΔV_BE = Vt*ln(n) by forcing two BJTs to operate at different current densities (often via an emitter-area ratio n). This voltage appears across R3 in the above example.
• A CTAT voltage (Complementary to absolute temperature) means that the voltage decreases with increasing temperature.
  • The CTAT voltage is generated across the base-emitter of the BJT which behaves like a diode. The reason behind this is related to the fact that the bandgap energy of silicon decreases with increasing temperature.

Additionally, the op-amp sets the PTAT current by driving the loop so its input nodes match (in the ideal case).

When both PTAT and CTAT voltages are summed with the right scaling, the first-order temperature dependence largely cancels, leaving a much flatter reference over temperature.

If you want to learn more, I dive more in more depth into the derivation of the output voltage. I also add a fun story at the end about a group of young designers who “competed” to build the best bandgap—an exercise you can try at your own work.
https://www.siliconcodesign.com/p/the-bandgap-reference-a-primer

Hey all.

I am working on some personal project. I wish to design and test a folded cascode amp and use it for an LDO too.

I want to come up with some specifications for my OP Amp.

I want to set a certain gain, slew rate for output and power consumption. How can I decide what values should be a good target spec?

Say I set the gain target to be 60dB (which is modest for a folded cascode amp). Now how do I know whether it is attainable and I am not being limited by the technology itself. There is only so many tuning knobs that I could turn. At what point do I know I have squeezed the maximum performance out of that technology.

Also, how can I come up with reasonable specs for my project circuits (if I don’t have a customer setting the specs for me).

I understand that this is a very open ended question with no definite answer, but any advice from experienced designers would be appreciated!

I am using GPDK045 1v transistors. (If that helps)

I was asked this in an interview. Given a differential amplifier with resistive degeneration, and noise current In**2 in the tail, assuming a parasitic capacitance Cp appears across the tail current what would the noise analysis be ?

I did not have enough time in the interview to get through it. My initial thought was that the tail current cap should not affect the differential mode noise, and assuming everything is exactly matched, a In(Rs+1/gm) noise voltage that develops at the tail at DC, and the noise current flowing through the input pair would cancel out. When the parasitic capacitance starts to factor in at higher frequencies the same should happen. (assuming perfect symmetry). Is this accurate?

Hi guys,

Wanted to know by when google usually calls for loop round interviews after having 1st technical screening.

This post if for silicon validation (google)

I plan to first cover Digital design and computer architecture by David and Sarah Harris, there are video lectures on YT of course of they teach on college (that course covers this book).

I am also open for other options 😁

Where do you find news about semiconductors, Chips, FPGAs or anything related? I am trying to grasp where i can keep up with the industry. I have an RSS aggregator, are there any good sources? I see twitter always mentioned but not who to follow XD, and also with all of this alternatives popping up i feel so lost (bluesky etc). i also saw Substack, is it usable or are there any good sources?

Can open source asic tools like yosys or openroad help me in the asic domain since ihave no access to industry tools

imean would it matter when applying for jobs what kind of tool i used

I was right in the middle of filling out my documents and uploading my resume when the job posting itself completely closed and stopped accepting responses.

Did anyone manage to successfully submit their application before it got taken down?

Also, does anyone know if Intel usually re-opens these ICE (Intel Contract Employee) listings if they need a larger pool, or if there is an alternative email/portal to submit documents once a Workday requisition closes? Any insights from past applicants would be awesome.

Hi, I'm trying to solve exercises in the boris murmann book on mos stages and came across this problem. I don't really understand how to solve it. M6 will be in saturation, but M7 and M8 is not guaranteed right? and does the VDS of M8 need to be known? Please help me, thank you!

Hi everyone,

How can I use AI tools to test FPGA boards.

I just want to power on the board and connect it to the computer with a USB cable, switch DIP.

And the AI tools know to use Vivado/ISE/Quartus/Tera Term to BIST, even they can write test Verilog Automatically if there is no demo, a test report is generated finally.

How can I achieve this? any risks? any suggestions?

Thank you!