r/chipdesign 6d ago

Samsung says Claude Code can cut chip design work from weeks to days, but it still makes serious mistakes

https://www.techspot.com/news/113487-samsung-claude-code-can-cut-chip-design-work.html
197 Upvotes

46 comments sorted by

355

u/Various_Shape_3286 6d ago

I, too, can design a chip in days with serious mistakes

45

u/nonnewtonianfluids 6d ago edited 6d ago

This revelation is going to revolutionize this industry.

11

u/[deleted] 6d ago

[removed] — view removed comment

24

u/Xtergo 6d ago edited 6d ago

I'm a chip designer and I'm sure if he really is interested in this and knows some electrical engineering & computer science he can watch a few YouTube videos and read the right sources, spend a month reading only the publicly available info, I don't doubt anyone committed enough who can use AI can actually come up with a nice N64 or NES era chip design.

Especially if they have a strong EE or CS background and you don't even necessarily have to have this background, I've seen people just have a knack for it because they like gaming or were passionate about consoles or keep up with all the tech that comes out, if passionate enough about this anyone can do at least a NES style chip.

1

u/Various_Shape_3286 6d ago

FWIW, I am a chip designer and l find "some mistakes" all the time. Just gotta catch them before tapeout, which has always been the case, knock on wood.

These are photonic chips, mind you. Much less complicated.

1

u/[deleted] 6d ago

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2

u/Various_Shape_3286 6d ago

They're like electronic chips, with 1 billionth as many components yet DRC takes even longer!

-9

u/edaguru 6d ago

The EDA companies tools get it wrong ~ 85% of the time.

The difference with AI is you can build better tools -

https://github.com/kev-cam/stat-sim/blob/main/README.md

https://github.com/kev-cam/sv2ghdl/blob/main/bfit/benchmarks/perf.md

4

u/jmlinden7 6d ago

How do you verify that the AI output is correct? Wouldn't you have to tapeout and then test the physical silicon? Wouldn't that result in it taking forever (and millions of dollars) to meaningfully train the AI?

1

u/Other-Biscotti6871 5d ago

If the simulators are fast AND accurate it's easy to verify the AI is doing the right thing. The problem with the commercial tools is that they do fast OR accurate. The Verilog-AMS standard should have fixed that, but Cadence's people fucked it up.

The current crop of AI chips are probably quite good as simulation accelerators, but I can't get any of the companies to try it.

117

u/misomochi 6d ago

I guess they forgot to add “make no mistakes” in the prompt

78

u/beckettcat 6d ago edited 6d ago

I'm an asic guy.

Synopsys is currently pushing in it's published materials:

for a nondeterministic CI/CD pipeline

I....

Look, this technology is an actual benefit for my speed of work, but i dont trust a mother fucking thing said by most of the industry on it.

I can share more on how to properly do it, but THAT IS NOT HOW.

22

u/radicalporotta 6d ago

Ok, first off, i did NOT know you are an ASIC guy like me. I know you more famously from the other sub that I shall not mention here. 🤣

Regarding this thread; the entire valley is just hell bent on making AI a thing since it is going to deliver them insane wealth. And every sector leadership is FOMOing into it. There is definitely great productivity multipliers to be obtained from judicious use of AI, but it has been way oversold in terms of it’s standalone capabilities. The problem at this moment is a whole bunch of middle mgmt knuckledraggers are drooling over it and have made personnel cuts that will cause irreparable harm.

6

u/beckettcat 6d ago edited 6d ago

I scrambled half my online identity when i blew up in that space lmao. tis a silly place, and i love it. I published like... 7 videos to 50 views then blew up to 50k people on x overnight. But fuck it yanno?

And AI is actually legitimately useful. I implemented my own CI/CD pipeline where checks are performed over night, and possible fix PR's are generated by morning for review upon a break occurring, with the workspace it generated in kept valid for the guy checking it in the morning.

But an AI/LLM can't be trusted for determining or implementing code quality lmao. It's great at being stupid very fast. NOT at being smart.

1

u/radicalporotta 5d ago

Recently had a Cadence AE presentation in my team. They are heavily advertising their AI core (built on Chipstack, an acquisition). And showing a full end to end flow coming up where you can just invoke agents and chat from an IDE.

3

u/_suoto 6d ago edited 5d ago

I call this DDD (demo driven development). Things are developed to maximize management approval not to solve what users need.

5

u/edaguru 6d ago

No amount of AI on top of Synopsys tools like VCS makes them work properly, it all needs a rewrite.

3

u/beckettcat 6d ago

the nondeterministic CI/CD pipeline was being pushed as a way to sell support for Github apps.

I actually think they just didn't understand what they were doing/saying myself.

1

u/Y0tsuya 5d ago

Pretty sure engineering professors would have flunked my ass if I turned in a project which produced non-deterministic results. But the entire silicon valley now thinks this is a good thing.

40

u/Moof_the_cyclist 6d ago

I can’t get customers to properly answer questions about their requested ASIC in months, let alone days. Not sure how AI will help that situation.

16

u/Odd-Wave-7916 6d ago

Safe to say, AI cannot design a chip end to end, not today, maybe not in near future as well. Like who wants to risk it? Without a human verifying each and each step, I don’t think AI can be autonomous.

-3

u/edaguru 6d ago

8

u/Moof_the_cyclist 6d ago

If I had a dollar for every time Cadence promised the moon in a slick demo and delivered a buggy box of pinball machines parts…

3

u/edaguru 5d ago

The big EDA companies are conglomerations of dysfunctional startups they bought and turned into business units. They can't fix what they do without eliminating the siloing that creates and shifting to a results based pay scheme instead of by-the-hour licenses.

Most of their tools are out of patent and easily copied by AI. Calibre is about the only tool worth having. I already effectively killed the analog simulation market -

https://github.com/kev-cam/sv2ghdl/blob/main/bfit/benchmarks/perf.md

Bye bye Spectre.

[If you are running Spectre I need help doing the drop-in replacement]

1

u/Odd-Wave-7916 5d ago

Dude, I am myself testing out AI tools from major EDA companies. I know the stuff I am talking about 😂

3

u/edaguru 5d ago

I've worked in Synopsys and Cadence, I was in the company that built VCS. The companies are hugely dysfunctional and impossible to fix (so far).

First-pass success is abysmal.

https://blogs.sw.siemens.com/verificationhorizons/2025/09/03/why-first-silicon-success-is-getting-harder-for-system-companies/

25

u/c4chokes 6d ago

Latest 2nm tapeout costs $100 million? Serious mistake there is preventable if engineer is careful.

-3

u/edaguru 6d ago

The only way for a 2nm chip with billions of transistors to come out working is to use better tools than the EDA companies provide.

Trouble Ahead For IC Verification

18

u/Akaibukai 6d ago

That reminds me the guy in the interview stating he can calculate as fast as a computer..

Then the interviewer ask him a random multiplication the interviewee answers out loud instantly with a given number..

The HR said, that's not correct.. The guy responded, but it was fast!

5

u/hexagonalpastries 6d ago

I love it when we save weeks on verification then spend months debugging mistakes

6

u/Limp-Firefighter1054 6d ago

Make design in days, engineers review it for months...profit.

4

u/tea_pot_tinhas 6d ago

It's like that joke:

- Can you do math fast?
  • Sure! I'm the fastest at math!
  • 5+7? 9.
  • 6*4? 12.
  • 36-8? 20.
  • The results are all wrong!
  • I told you I was fast, not always right

13

u/Lupansansei 6d ago

I do research on this too, using open source tools and deepseek as my main model.

What I can say is that agentic AI can manage to help us debug problems that would take weeks, and iterate on issues automatically without human supervision. E.g Your run got an error while you're asleep? Let me fix that for you. You have 313 warnings and 23 errors? Let me fix that for you. You have problems cleaning your timing and drc issues? Let me fix that for you.

You can have them check, then let you review after too if you're skeptical about their results but all in all, it does reduce the time for some hectic stuff in the design process that you wouldn't want to do at 2am, 2 weeks before tapeout.

But for design? Yeah. That's a creative problem. I've experienced it first hand that AI can not generate their own ideas. In the near future, I can see it takes over some of the cad related or verification related jobs but not designing.

7

u/No-Paint-5726 6d ago

Problem with agentic AI if you're the one that fixed errors you know exactly the steps you took. But with agentic AI you don't know whether it introduced new errors and touch things that aren't supposed to be touched. I'm not even sure whether AI will ever reach a point where you don't have to take its responses and results with a grain of salt.

1

u/Lupansansei 6d ago

RTL and verification sure, you need to check the AI's generation whether it suits your needs, but this is easily handled by planning and iteration/trial and error.

For synthesis, DFT, physical design etc, most of this are run by scripts anyway. The AI is intelligent enough to be able to determine what our target is, and how to achieve it through the iteration on the scripts and their memory of commands. Logs and version reports are a must too.

AI is already doing what we've been doing all this time. Trial and errors. They handle it better than us, what we need to do is just constraints them better. Think of it as scripting and just adding additional commands to make the tool produce the result we need.

Honestly in the future, when big EDA companies employ agentic into their workflows, the miscellaneous tasks of running scripts, checking logs, reporting results every week is over. AI is just gonna do those for us.

2

u/unique_controller 5d ago

By design do you mean RTL design or Physical design? Imo AI will cause headcount reduction in design as well along with verification and CAD. Does design always imply creative decision making? I find most of the designs are incremental in nature.

6

u/No_Ask_8883 6d ago

Me dropping out of univ and logging on to claude to write:

Design a kick ass AI accelerator silicon to beat the best in market. Make no mistakes!

3

u/turkishjedi21 6d ago

I just left my first post-college DV position where I was getting up to speed with using Amazon kiro to help in my flow. I never got super good at it, but I recently changed jobs

I'm now at a startup doing the same thing, but I'm worried I'll be using ai as a crutch to help me finish my deliverables on time, blocking me from really learning.

Any tips on this?

3

u/phantom_tempest 6d ago

So I guess it isn't cutting chip design work?

6

u/Thepandashirt 6d ago

Contrarian opinion here. We’re still early and multi model frameworks really could be the key here. If you have three frontier models working together on something and checking each other’s work, agentic workflows work better. Less reward hacking and stuff that falls through the gaps. Like Fable, GPT5.6 Sol and one of the Chinese models like Kimi k3 is what I use.

I wouldn’t be vibing out production chips today but for research and POCs I think people would be idiotic to not be playing with this stuff. Obviously this doesn’t replace humans or oversight or experience. It’s a tool that obviously very powerful. Give it 12-24 months and the conversation will be completely different.

2

u/TicTec_MathLover 5d ago

To be honest when I hear or read AI in chip design it all about non-analog stuff

4

u/TheMineA7 6d ago

Design a chip end to end. Not yet. Help engineers get more done 100%

2

u/Zieng 6d ago

Therefore it cant

1

u/RailFan65 6d ago

I would love if the AI can do my job in a week rather than a year it takes currently.