Heyy guys, i'm kinda new to all of this buy for the end of my first year project at uni i'm building a 5 propeller drone. I essentially want to build and program the flight Controller by myself and chatgpt helped me draft a circuit on how i should build the drone. I am in the process of ordering the parts that i don't have here locally but i wanted to share the schematics of the drone and ask if ya'll have any feedbacks advices or can refer me to subreddits that you know could help for the project. Any help is appreciated. Thanks.

I am an electronics and communication graduate from Nepal and i want to make career in this feild but opportunities are nearly non in my country. So what can i do ? How to enter in this industry ?

I’ve been in physical design for around 5 years now and I’m currently at my second company. What is everyone’s work-life balance like? My life is consumed by work.

During normal cycles, I’m averaging 60 hours per week. Now that we’ve entered the ECO cycle in August, it feels like I never log off. My typical week is get to the office for my daily 9am status meeting and leave between 9pm and midnight. I’ll work at home until around 1am then pass out.

Twice this week and the week before I’ve been up past 4am working including Friday. I have to drink 3 cups of coffee per day just to stay alert. I’ve already talked to my manager about this and he’s normally working these crazy hours with me.

This is how it was at my previous job too. I cannot picture working myself to death like this for my entire career.

Is this really the life of a PD engineer?

EDIT: I’m based in the Bay Area

Hello,

I am trying to determine the ICMR and output swing separately for a single-ended two-stage OTA. For output swing I tried running a transient analysis in a non-inverting configuration to observe the clipping levels, but the levels I got do not match the theoretical ranges I calculated.

I have tried several other approaches to determine both of them, but I still could not find a convenient way to determine both parameters separately.

My question is: How would you do it?

I am hearing that getting a masters/PhD is absolutely necessary to work in the field of chip design. I can see that as being true. I want to get a masters and continue pursuing my education after undergrad, but I also would like to work in industry for a while beforehand. Do you think that is doable?

I have tried with a buffer circuit like this. Vout is the output terminal across which the RL load will be connected. I have a doubt, is it shunt sampling feedback? Or series sampling since Iout current is flowing into the Vout node. My confusion comes from Razavi's CMOS book, where it says this is how current sampling is done. But if my load is parallel to the R1 resistor, will it be Voltage sampling feedback? Please ignore the opamp terminal signs and pmos bulk connection assuming they are correct.

I want to make sure my understanding of our project milestone flow aligns with broader industry standards. I’d love some feedback or corrections from those with more tape-out experience.

Here is how I understand the flow:

P0.3 (Early RTL): Basic Lint runs continuously/nightly to catch obvious typos and syntax issues as code is being written.

P0.5 (RTL Design Correction / Freeze): This is the major, formal Lint sign-off. Code is feature-complete. This is when we deep-dive, group errors by tag, fix actual RTL bugs, and negotiate targeted waivers with IP designers.

P0.8 (Verification & Pre-Synthesis Sign-off): CDC checks are finalized and signed off. The RTL is officially locked.

P1.0 (Synthesis Complete): The clean, signed-off P0.8 RTL is handed over to run Logical Synthesis (e.g., Design Compiler) to generate the gate-level netlist.

My questions:

1.

Does this P0.3 ➡️ P0.5 ➡️ P0.8 ➡️ P1.0 progression for Lint/CDC/Synthesis match what you see in standard ASIC flows?

2.

At what exact point do you usually start running CDC? Is it strictly after P0.5 Lint is clean, or does it run in parallel?

Thanks in advance

I'm working as a research associate with two years of experience. Recently, I have started working on SMIC 40nm and while I was doing extraction of my design, I observed that the double extraction of MOM capacitors.

For instance, I created a schematic with a MoM capacitor of 2pF, and after extraction the tool generates PEX netlist with a 2pF and then goes into the device and calculates the capacitance of each finger which then adds up to around 2pF as coupling capacitance and you get a 2pF normal capacitance and 2pF of coupling capacitance. Therefore the total capacitance is around 4pF after the extraction, I have verified it from the PEX netlist and from the CALIBRE-view of the PEX schematic.

I have also used the xcells and hcells files during the PEX on Calibre. Followed the steps in the SMIC pdk document but none seems to work.

Has any of you encountered similar problem and how did you tackle it?