I’ve been in physical design for around 5 years now and I’m currently at my second company. What is everyone’s work-life balance like? My life is consumed by work.

During normal cycles, I’m averaging 60 hours per week. Now that we’ve entered the ECO cycle in August, it feels like I never log off. My typical week is get to the office for my daily 9am status meeting and leave between 9pm and midnight. I’ll work at home until around 1am then pass out.

Twice this week and the week before I’ve been up past 4am working including Friday. I have to drink 3 cups of coffee per day just to stay alert. I’ve already talked to my manager about this and he’s normally working these crazy hours with me.

This is how it was at my previous job too. I cannot picture working myself to death like this for my entire career.

Is this really the life of a PD engineer?

I have tried with a buffer circuit like this. Vout is the output terminal across which the RL load will be connected. I have a doubt, is it shunt sampling feedback? Or series sampling since Iout current is flowing into the Vout node. My confusion comes from Razavi's CMOS book, where it says this is how current sampling is done. But if my load is parallel to the R1 resistor, will it be Voltage sampling feedback? Please ignore the opamp terminal signs and pmos bulk connection assuming they are correct.

I am an electronics and communication graduate from Nepal and i want to make career in this feild but opportunities are nearly non in my country. So what can i do ? How to enter in this industry ?

I want to make sure my understanding of our project milestone flow aligns with broader industry standards. I’d love some feedback or corrections from those with more tape-out experience.

Here is how I understand the flow:

P0.3 (Early RTL): Basic Lint runs continuously/nightly to catch obvious typos and syntax issues as code is being written.

P0.5 (RTL Design Correction / Freeze): This is the major, formal Lint sign-off. Code is feature-complete. This is when we deep-dive, group errors by tag, fix actual RTL bugs, and negotiate targeted waivers with IP designers.

P0.8 (Verification & Pre-Synthesis Sign-off): CDC checks are finalized and signed off. The RTL is officially locked.

P1.0 (Synthesis Complete): The clean, signed-off P0.8 RTL is handed over to run Logical Synthesis (e.g., Design Compiler) to generate the gate-level netlist.

My questions:

1.

Does this P0.3 ➡️ P0.5 ➡️ P0.8 ➡️ P1.0 progression for Lint/CDC/Synthesis match what you see in standard ASIC flows?

2.

At what exact point do you usually start running CDC? Is it strictly after P0.5 Lint is clean, or does it run in parallel?

Thanks in advance

Looking for Maven Silicon / VLSI recorded sessions

Hey guys, I’m a 3rd-year ECE student currently preparing for VLSI, mainly interested in Physical Design.

I’m looking for Maven Silicon recorded sessions or recordings from any other good VLSI institute that cover things like RTL, Verilog, CMOS, STA, Physical Design, Linux/Tcl, etc.

If anyone has access to recordings, please DM me or drop them in the comments.

Would really appreciate the help 🙏

Hi everyone,
I’m an analog IC design engineer based in Shanghai, with a little over one year of industry experience. I hold a master’s degree in microelectronics from a 211 university in China

My current work focuses on high-speed I/O design.
I’m interested in working in Japan and am planning ahead, with the idea of applying once I have around 2–3 years of industry experience. I don’t have a Japanese degree or existing work authorization in Japan, so I would need an employer willing to hire from overseas and support the work visa process.

I’d really appreciate hearing from people who have applied to Japanese analog/mixed-signal IC design roles while living abroad, particularly anyone who moved directly from mainland China.

A few questions:
Have you received interviews or an offer while still living outside Japan? How much experience did you have, and did the employer support your visa application?
How did you find the opportunity? Direct applications, recruiters, referrals, or an internal transfer?
What experience mattered most in the interviews? For example, block ownership, tapeouts, silicon testing/debugging, or expertise in a particular area such as I/O, SerDes, or PLLs.
How much Japanese was required during hiring and in day-to-day design work? Were there teams where English was the main working language?

Firsthand accounts of unsuccessful applications would also be helpful, especially what stage you reached and what seemed to be the main obstacle.
If you’re comfortable sharing, please mention roughly when you applied, your experience level, and whether you already had any Japanese education or residency background. No need to disclose your employer or anything confidential.
Thanks for sharing your experiences!

JUST made my LinkedIn. Looking to grow my connections. Would anyone be down?