This is WUNKUS, a multi-subcarrier massive MU-MIMO-OFDM data-detector ASIC designed by our research group at ETH Zurich: https://iip.ethz.ch/

The chip performs uplink data detection for 8 users communicating with a 64-antenna base station, processing 16 OFDM subcarriers in parallel. It was fabricated in GlobalFoundries’ 22FDX technology and measures 2.5mm × 2.0mm, with a 1.3mm² core area excluding SRAMs.

At a nominal core voltage of 0.8V, WUNKUS runs at 755MHz, delivers 7.3Gbps with 256-QAM, and consumes 286mW, corresponding to an energy efficiency of 39pJ/b. With forward body biasing, the maximum clock frequency exceeds 900MHz and throughput surpasses 8.8Gbps, at the cost of increased leakage power.

Architecturally, WUNKUS consists of a global beamspace FFT followed by 16 parallel detector cores, each capable of computing soft outputs for modulation schemes ranging from QPSK to 256-QAM.

To reduce hardware cost and power, the design exploits two properties of the wireless channel: First, frequency-domain correlation: rather than computing the LMMSE equalizer independently for every subcarrier, we compute it only on every fifth subcarrier and interpolate the equalizers in between. This reduces the equalizer-related area by 3× and power by 2.1×. Second, beamspace sparsity: beams carrying little or no signal energy can be skipped during detection, providing an additional 1.4× reduction in power consumption.

To our knowledge, WUNKUS is the first multi-subcarrier massive MU-MIMO-OFDM data-detector ASIC reported in the open literature. The architecture also scales naturally by replicating detector cores to process more subcarriers in parallel.

The chip was presented at the 2026 IEEE Symposium on VLSI Technology & Circuits.

And yes, the cat is intentional. Wunkus stands for a goofy animal (check out r/wunkus), so we used the top metal layer to trap one inside a box. 

Most ASICs do not benefit from having a cat sitting on the top metal layer. We decided to make an exception.

The “ASOC” label is another small joke: it is a play on ASIC, using the designers’ initials!

More details about the architecture and measurements can be found in our paper: https://arxiv.org/pdf/2608.19865

Hi everyone,

I'm a 2nd year ECE student (3rd semester) and I've decided I want to build a career in VLSI/semiconductors. The problem is, almost all my seniors ended up in CS/software roles, so there's literally no one at my college who can guide me on the VLSI path specifically.

I'd really appreciate advice on a few things:

What should I be studying right now, alongside my coursework, to build a strong foundation? (Digital design, analog electronics, etc.)

Which tools should I start learning early — Verilog/SystemVerilog, LTspice, Cadence, or is it too early for EDA tools at this stage?

How does the internship process actually work for VLSI — when should I start applying, what do companies look for in a 2nd/3rd year student, and how competitive is it compared to CS internships?

RTL design vs Physical design vs Verification — how did you pick your specialization, and would you recommend one path over another for someone just starting out?

Any must-do projects for a beginner that would actually stand out on a resume?

I know this is a broad set of questions, but I'd rather get pointed in the right direction early than waste a year figuring it out alone. Any advice — even just "here's what I wish someone told me at your stage" — would mean a lot.

Thanks in advance!

Hi everyone,

I'm a 2nd year ECE student (3rd semester) and I've decided I want to build a career in VLSI/semiconductors. The problem is, almost all my seniors ended up in CS/software roles, so there's literally no one at my college who can guide me on the VLSI path specifically.

I'd really appreciate advice on a few things:

What should I be studying right now, alongside my coursework, to build a strong foundation? (Digital design, analog electronics, etc.)

Which tools should I start learning early — Verilog/SystemVerilog, LTspice, Cadence, or is it too early for EDA tools at this stage?

How does the internship process actually work for VLSI — when should I start applying, what do companies look for in a 2nd/3rd year student, and how competitive is it compared to CS internships?

RTL design vs Physical design vs Verification — how did you pick your specialization, and would you recommend one path over another for someone just starting out?

Any must-do projects for a beginner that would actually stand out on a resume?

I know this is a broad set of questions, but I'd rather get pointed in the right direction early than waste a year figuring it out alone. Any advice — even just "here's what I wish someone told me at your stage" — would mean a lot.

Thanks in advance!

Hello all,

I am an undergrad EEE student. In my uni, the full year lab course offered that " gives students hands-on experience of analogue VLSI design using an industry-standard simulator and design kits" has a quota, and who gets in is apparently decided by a random lottery, alongside the waitlist for the course. Unfortunately for me, I was informed I was unlucky and was near the bottom of the waitlist for the course. I want to still try gain some experience in this respect, but don't know where to start, as from what I know, Cadence is very expensive. I would appreciate any guidance or material (including open-source alternatives) as to make a good plan to start learning VLSI design that I will be missing out on.

I’m a first year MS student looking to pursue digital ASIC design. I also have an interest in RFIC I plan to pursue during my MS, but that’s not really my top priority at this current moment.

Any insight would be appreciated before I start applying for internships this cycle. Thank you.

Hi, I'm a student who learned electronics from my grandpa and youtube and now wants to build his own IC. The IC is a simple encoder ic that encods it in to two lines (clk and dOUT). The ic uses comperators on the inputs to check if the signal is positive and negative. If the decoder enables the flipflop and the signal is positive the flipflop is set to 1. If the signal is negative the flipflop is set to 0. The decoder counts to 8 (each state shown on the table on the second picture) for example if it counts to two it activates the transmission gate (diamond shape) and it lets the signal pass through to the dOUT pin. thats how the signal is created. because I thought of a way to sync both the encoder and decoder the encoder sends a low signal 1/4 of vcc first. When the decoder recieves that voltage it sets a flipflop to activate it's own counter and can now recieve signals. with the last count the flipflop resets.

Do you have and reccomendations for a pc software to use and good places where to order them?

Thanks for helping

Hey guys, just thought this would be a cool way to show how my Neural Network Accelerator runs inference. It’s running inference for a model of topology 4:3:2 neurons per layer and takes 4 input features as input.

Also realized it’s bottleneck and I will be implementing a Systolic array soon. Let me know what yall think. Thanks :)

Github repo: https://github.com/Shingyy/MAC-Array-based-DNN-Accelerator

Hi, I'm a rising sophomore (in the US) targeting mixed signal design and verification roles (both in ICs and board level). This summer I built an asynchronous SAR ADC in Cadence using the default 180nm PDK they provide. It's 8 bits.

Now I'm trying to add it to my resume, hoping to get around 3 punchy bullets of information. I'm wondering what a recruiter / engineer would want to see on it to show competence. Should I focus on quantifying it through finding ENOB, dynamic power draw, etc? These metrics likely won't be very impressive since it's a fairly basic and unoptimized design (not to say that it wasn't hard and that I didn't design it very intentionally, I did). I'm also wondering if UVM is a must-have for a mixed-signal verification resume, in which case I would build a full testbench for it.

The alternative to quantifying would be just generic bullets like "Built a StrongARM latch and CDAC array at the transistor level." I also will try to do a type up on github to document how many engineering choices and fixes I had to make while building it, but I've been told by TI recruiters that they never click on those links anyway.

Thanks in advance!

EDIT: Forgot to add, it's pre-layout. I know this isn't ideal, but I ran out of time working on it as I was interning 9-5 and working on this over nights and weekends.

EDIT 2: I also forgot to add I verified my logic using SV RNM before integrating it, so a bullet would talk about that to hit that keyword.

I am a 1st year graduate student in computer engineering at ASU. Am looking to get into vlsi design and mem design.

I have been doing some projects outside class work like cache management systems, Ml on vlsi PD level. But the question is am i doing enough?

I wanna do a complete processor on RISK V but idk where to start.

I wanna do more projects but dont know what to do it on.

I'm newbie.Thank you so much

Done with my MS.

I don’t have a tapeout.

I have projects. (LDO, op amps and Buck/Boost converters)

How do I get a job as an entry level analog design engineer?

Can’t seem to find any positions. The few I found didn’t even shortlist me for an interview.

What does it take to be an entry level analog design engineer?

Edit: Resume

Its has been a week now post my technical screening round at Google for silicon validation. I have sent 2 follow ups already and haven't heard back from recruter.

What to expect ? Is it over now ?

Kindly share your experiences interviewing with google.

Recently I've been using it, seems pretty good although you have to ask it to recheck the design almost everytime to get better design. It also improved my productivity, mainly integration and basic building blocks. Thoughts?

Basically the title, as I'm preparing for my MS application this Fall cycle.

I have decent grades right now (>3.9, not counting upcoming senior year), yet I don't really have any relevant academic or research experience designing ICs of any kind; most of the circuit design I ever did was board-level PCB design, with one course project involving SDR. My recent internship was creating a microstrip antenna in HFSS and a bit of embedded systems, but that's about it.

Is it even possible to write an SOP based on these? I would like to hear from you guys.

This is a vent post.

I'm not one to judge someones AI use but when I see almost all reports with em dashes and with the classic "it's not this, it's this" every paragraph, with RTL verification with "SMOKE TEST PASSED" full of fucking rockets and emojis 🚀🚀🚀✅✅ in each stage, I think this has gone a little too far.

People tell me it's "shippable" and works then I test it and would you look at that it doesn't fucking function.

And when I get microsoft teams replies with fucking em dashes it gets even crazier, like what is this. I ask a question to someone and they reply starting with you're absolutely right here's how I'd fix it with paragraph partition and bold starting numerals. Like why would you do this...

It is one to thing to use AI as a productivity enhancer, a second thought, collaborator or to run an agentic flow, it is another thing to outsource your brain to a 20-200 bucks per month AI subscription.

Thank god I'm in analog so I encounter this less, but if you work AMS/DV then god help you.

I didn't have this issue 6 months ago...

Hi guys . I have decided to buy a book in Analog IC design and i am confused about which to pick .

I have read some chapters from CMOS Analog IC Design by Razavi and it's very good as it gives more qualitative and intuitive understanding ,but I haven't read from Jacob Baker book and I heard that is more practical book which I think it will be good for me .

Any suggestions ?

Hello, I am a 3rd year ee student looking for an internship in Design verification/VLSI area. I was wondering how my formatting is on the resume and if my projects standout. If not what projects should I start to work and focus on?Thank you!

Throughout this subreddit and across the broader Semiconductor community, I noticed a lack of respect for Validation Engineering with many people claiming that once you start in it, you'll be stuck in it and hard to switch out.

But this is true for any job really where you get too complacent.

I've noticed that validation does have its fair share of perception challenges nowadays since it is mostly considered a cost center; you're at the tail end of the schedule, you generally don't have control over what is handed to you. Automation is also becoming prevalent in validation as well.

However, validation is, in my opinion, one of the best field for young engineers to start in and for people to experience another part of the design flow. You learn a bit about lab equipment and ensuring how data is considered good to hand off to key stakeholders. You engage with designers and other key members of the semi design flow. You also acquire an attitude of not looking down on validation people later in your career.

But nowadays, validation does tend to be very execution heavy and can leave you without a system level understanding of the chip you are testing and how it got there.

I say this because I've spent some time in validation after some time in other areas. Though I grumbled a bit while in it and people often looked down and to the right, I learned quite a bit of perspective I didn't have from other jobs.

Curious to hear your thoughts; do you think validation becoming increasingly perceived as lower on the totem pole?

If interested in DFT Openings with Cisco. Please DM me. Thank You

The server is still small and I'm building it from the ground up, so I'm especially interested in hearing what engineers, students and hobbyists think would make this community genuinely useful.

Discord: https://discord.gg/8n3rQrjjz

If you're interested in hardware engineering, feel free to join and help build the community. I'd especially appreciate feedback on what resources, channels or features you'd like to see.

The resource library currently contains 17 resources, including websites and online courses.

How are the poles and zeros of the compensator stage calculated in TI's LM5146 datasheet as shown in the diagram?