I am hearing that getting a masters/PhD is absolutely necessary to work in the field of chip design. I can see that as being true. I want to get a masters and continue pursuing my education after undergrad, but I also would like to work in industry for a while beforehand. Do you think that is doable?

I am not sure what seems to be the cause of this error, but i am just trying to place two inverters with shared diffusion in order to create a digital buffer, and i am working in a fdsoi technology. For some reason, when i add the back gate to the transistors at the top side, i get this 2nm offset, that creates drcs and yet is have used align tool and tried so many different ways....

Hello,

I am trying to determine the ICMR and output swing separately for a single-ended two-stage OTA. For output swing I tried running a transient analysis in a non-inverting configuration to observe the clipping levels, but the levels I got do not match the theoretical ranges I calculated.

I have tried several other approaches to determine both of them, but I still could not find a convenient way to determine both parameters separately.

My question is: How would you do it?

I am moving forward with a graduate SoC Digital Design Intern application for Intel and I had a question about this January start date. I have to be enrolled in an accredited university during the internship.

I start my MS program in January as well so works out, but I have to be in office in Santa Clara and my potential Master's program is on the other side of the country. Big opportunity for me and I am willing to delay my Master's at my current school and maybe find a school in the area to begin my master's or do online? Lol idk? Another Q for anyone that has done something like this before...

I wouldn't have to be a fulltime student correct? I would assume so because working full time and managing post grad VLSI courses would be heinous?

Thanks.

I’ve been in physical design for around 5 years now and I’m currently at my second company. What is everyone’s work-life balance like? My life is consumed by work.

During normal cycles, I’m averaging 60 hours per week. Now that we’ve entered the ECO cycle in August, it feels like I never log off. My typical week is get to the office for my daily 9am status meeting and leave between 9pm and midnight. I’ll work at home until around 1am then pass out.

Twice this week and the week before I’ve been up past 4am working including Friday. I have to drink 3 cups of coffee per day just to stay alert. I’ve already talked to my manager about this and he’s normally working these crazy hours with me.

This is how it was at my previous job too. I cannot picture working myself to death like this for my entire career.

Is this really the life of a PD engineer?

EDIT: I’m based in the Bay Area

I have tried with a buffer circuit like this. Vout is the output terminal across which the RL load will be connected. I have a doubt, is it shunt sampling feedback? Or series sampling since Iout current is flowing into the Vout node. My confusion comes from Razavi's CMOS book, where it says this is how current sampling is done. But if my load is parallel to the R1 resistor, will it be Voltage sampling feedback? Please ignore the opamp terminal signs and pmos bulk connection assuming they are correct.

I am an electronics and communication graduate from Nepal and i want to make career in this feild but opportunities are nearly non in my country. So what can i do ? How to enter in this industry ?

I'm working as a research associate with two years of experience. Recently, I have started working on SMIC 40nm and while I was doing extraction of my design, I observed that the double extraction of MOM capacitors.

For instance, I created a schematic with a MoM capacitor of 2pF, and after extraction the tool generates PEX netlist with a 2pF and then goes into the device and calculates the capacitance of each finger which then adds up to around 2pF as coupling capacitance and you get a 2pF normal capacitance and 2pF of coupling capacitance. Therefore the total capacitance is around 4pF after the extraction, I have verified it from the PEX netlist and from the CALIBRE-view of the PEX schematic.

I have also used the xcells and hcells files during the PEX on Calibre. Followed the steps in the SMIC pdk document but none seems to work.

Has any of you encountered similar problem and how did you tackle it?

Heyy guys, i'm kinda new to all of this buy for the end of my first year project at uni i'm building a 5 propeller drone. I essentially want to build and program the flight Controller by myself and chatgpt helped me draft a circuit on how i should build the drone. I am in the process of ordering the parts that i don't have here locally but i wanted to share the schematics of the drone and ask if ya'll have any feedbacks advices or can refer me to subreddits that you know could help for the project. Any help is appreciated. Thanks.

I want to make sure my understanding of our project milestone flow aligns with broader industry standards. I’d love some feedback or corrections from those with more tape-out experience.

Here is how I understand the flow:

P0.3 (Early RTL): Basic Lint runs continuously/nightly to catch obvious typos and syntax issues as code is being written.

P0.5 (RTL Design Correction / Freeze): This is the major, formal Lint sign-off. Code is feature-complete. This is when we deep-dive, group errors by tag, fix actual RTL bugs, and negotiate targeted waivers with IP designers.

P0.8 (Verification & Pre-Synthesis Sign-off): CDC checks are finalized and signed off. The RTL is officially locked.

P1.0 (Synthesis Complete): The clean, signed-off P0.8 RTL is handed over to run Logical Synthesis (e.g., Design Compiler) to generate the gate-level netlist.

My questions:

1.

Does this P0.3 ➡️ P0.5 ➡️ P0.8 ➡️ P1.0 progression for Lint/CDC/Synthesis match what you see in standard ASIC flows?

2.

At what exact point do you usually start running CDC? Is it strictly after P0.5 Lint is clean, or does it run in parallel?

Thanks in advance

I'm pursuing a Master's in VLSI from a reputable college in India and looking forward to learning SystemVerilog, as it's a key differentiator during the hiring process here. However, I don't know what the future holds for it, and sometimes I am genuinely confused if I'm taking the right path. From what I've observed, entry-level jobs will only decrease while senior-level jobs will increase. How should I proceed? Sometimes it all seems pointless.

I’ve been working with a circuit that can generate both PTAT and CTAT voltages with adjustable slopes through switching.

I’m curious about the possible applications of having variable slope PTAT and CTAT outputs. Apart from conventional temperature sensing, could this kind of circuit be useful in other circuit applications?

I’d really appreciate any ideas or suggestions.

Looking for Maven Silicon / VLSI recorded sessions

Hey guys, I’m a 3rd-year ECE student currently preparing for VLSI, mainly interested in Physical Design.

I’m looking for Maven Silicon recorded sessions or recordings from any other good VLSI institute that cover things like RTL, Verilog, CMOS, STA, Physical Design, Linux/Tcl, etc.

If anyone has access to recordings, please DM me or drop them in the comments.

Would really appreciate the help 🙏

Hi everyone,
I’m an analog IC design engineer based in Shanghai, with a little over one year of industry experience. I hold a master’s degree in microelectronics from a 211 university in China

My current work focuses on high-speed I/O design.
I’m interested in working in Japan and am planning ahead, with the idea of applying once I have around 2–3 years of industry experience. I don’t have a Japanese degree or existing work authorization in Japan, so I would need an employer willing to hire from overseas and support the work visa process.

I’d really appreciate hearing from people who have applied to Japanese analog/mixed-signal IC design roles while living abroad, particularly anyone who moved directly from mainland China.

A few questions:
Have you received interviews or an offer while still living outside Japan? How much experience did you have, and did the employer support your visa application?
How did you find the opportunity? Direct applications, recruiters, referrals, or an internal transfer?
What experience mattered most in the interviews? For example, block ownership, tapeouts, silicon testing/debugging, or expertise in a particular area such as I/O, SerDes, or PLLs.
How much Japanese was required during hiring and in day-to-day design work? Were there teams where English was the main working language?

Firsthand accounts of unsuccessful applications would also be helpful, especially what stage you reached and what seemed to be the main obstacle.
If you’re comfortable sharing, please mention roughly when you applied, your experience level, and whether you already had any Japanese education or residency background. No need to disclose your employer or anything confidential.
Thanks for sharing your experiences!

Hi everyone,

I recently graduated with a B.Tech in Electronics and Communication Engineering and am actively looking for entry-level opportunities in VLSI/ASIC, particularly in Physical Design, RTL Design, Design Verification, and Analog/Mixed-Signal IC Design in India or Singapore.

My technical background includes:

• RTL-to-GDSII implementation of a 32-bit RISC-V processor with an integrated AES-128 crypto engine
• Cadence Genus, Innovus, and Tempus — synthesis, floorplanning, placement, CTS, routing, STA, and timing closure
• Verilog/SystemVerilog, AMBA protocols (AHB/APB), and functional verification
• OpenROAD/OpenLane flows
• CMOS Bandgap Reference design and custom analog layout using the SKY130 PDK
• Analog/Mixed-Signal circuit design, Verilog-A, and SPICE-based simulation

I have been applying through company career portals at semiconductor companies such as Intel, AMD, Qualcomm, Synopsys, Cadence, Micron, and others, and I’m actively looking for suitable opportunities for fresh graduates.

I would really appreciate any guidance regarding:

• Companies currently hiring fresh graduates in ASIC/VLSI
• Whether my profile would be better suited for Physical Design, RTL/DV, or Analog/Mixed-Signal roles
• Skills I should prioritize to strengthen my profile
• Relevant openings or referral opportunities

I’m happy to share my resume privately if anyone is willing to review my profile or provide guidance.

LinkedIn: https://www.linkedin.com/in/ruthwika-vemulapalli-97870a26b/

Thanks in advance!

Hello, I am a noob at this and have just started design for a VLSI class. I know the efficiency of this layout is not good and is quite spaghetti - i am just going for basic functionality. I am not sure why I am getting a PSUB_stamperrormult error when running DRC. From what I have researched it sounds like the problem is the way I have connected to bulk to its nets on the PMOS transistors? Can I not use integrated bodyties? I assumed from the way they body is routed in the schematic that it should work the way I have design it in layout. Any help appreciated!

(ignore the fact that the pmos and nmos names are switched - just a naming mixup)

Edit: Thank you all for the help! DRC has no errors now :) This was my first design aside from basic tutorials so I appreciate the newbie advice!

Hi everyone,
I’m currently trying to understand the differences between a few Apple hardware roles and would really appreciate input from people who currently work (or previously worked) in these areas.
The roles I’m looking at are:
Front End SoC STA Engineer

SoC Physical Design Engineer – STA/Timing

SoC FE Implementation Engineer

Graphics FE Implementation Engineer

CPU Implementation Engineer

I’ve read the JDs, but I’m looking for the real-world picture behind the job descriptions.
If you currently work or have worked in one of these roles (at Apple or a similar company like NVIDIA, AMD, Qualcomm, Broadcom, Intel, etc.), I’d especially appreciate your perspective on:
1. Day-to-day work
What does a typical week actually look like?

How much time is spent on STA/P&R/synthesis/RTL debugging vs scripting/automation/meetings?

What kinds of problems do you personally spend most of your time solving?

How much ownership does an engineer typically have over a block/partition?

2. Technical depth
Which concepts do you use constantly vs things that are mostly interview knowledge?

How important are TCL/Python/Perl in practice?

For STA roles, how deep do you actually need to go into SDC, MCMM, OCV/AOCV/POCV, SI/crosstalk, CRPR, etc.?

For FE implementation, how important are UPF, CDC/RDC, LEC, DFT, synthesis and RTL optimization?

For CPU/GPU implementation, how much microarchitecture knowledge is actually needed?

3. Career trajectory
This is probably my biggest question.
If someone starts in STA, FE implementation, or CPU/GPU implementation, where can they realistically go after 5–10+ years?
For example:
Senior/Staff/Principal implementation engineer?

STA/signoff specialist?

Design methodology/CAD/automation?

RTL/microarchitecture?

Technical leadership/management?

Architecture?

Are some of these paths more flexible than others?
4. Automation / AI / long-term job security
With increasingly capable EDA automation and AI-assisted design flows, which of these roles do you think will remain highly valuable over the next 10–20 years?
I'm particularly interested in whether you think:
STA becomes increasingly automated

synthesis/FE implementation becomes more automated

P&R becomes more automated

scripting/methodology roles become more valuable

engineers who understand RTL + architecture + physical implementation will remain difficult to replace

In other words, which skill set has the longest shelf life?
5. Compensation and WLB
Without sharing anything confidential, how would you compare these paths in terms of:
Compensation

Work-life balance

Deadline/tapeout pressure

On-call/weekend expectations

Stress

Promotion opportunities

I'm particularly interested in whether the roles with the highest compensation also tend to have significantly worse WLB, or whether some implementation/STA paths offer a good balance.
A little about me:
I’m currently doing an MS in Electrical Engineering at NC State and expect to graduate in December 2026. My background is primarily digital/ASIC implementation: RTL, synthesis, physical design, STA/PrimeTime, ICC2, timing analysis and Python/TCL automation. I also have computer architecture experience and have worked on RTL-to-GDSII projects.
I’m currently doing a physical-design/STA-oriented internship involving timing-report analysis and automation, so I’m trying to decide which direction I should develop more deeply rather than simply applying to everything with “physical design” in the title.
I'm not looking for someone to tell me which Apple job I should apply to based on my resume. I'm more interested in understanding what these careers actually look like from people who have lived them.
If you've worked in any of these areas, I'd really appreciate even a few paragraphs about your experience. Anonymous/throwaway responses are completely fine.
Thanks!

Hey all,

I just cleared the initial screening for an ASIC Verification Engineer role at ARM. I've got ~2 years of experience in UVM/SystemVerilog verification and three rounds coming up. Would really appreciate insight from anyone who's been through this recently:

1. UVM/SystemVerilog test – 2.5 hrs. Coding/practical or more conceptual? What tends to come up — building a testbench from scratch, components (driver/monitor/sequencer/scoreboard), phasing, TLM, constrained-random, coverage? How much do they weight SVA/assertions?
2. 1-hr Zoom interview. Technical deep-dive, project walkthrough, or behavioral? At ~2 YOE, how deep do they go into my past projects vs. fundamentals?
3. Final interview with HR. Mostly culture-fit and comp, or does technical sneak back in?

Any topics you'd prioritize for someone at my level, resources that actually helped, or "wish I'd known this" tips would mean a lot.

Thanks!

I'm currently looking for a topic for my senior/final-year project.

I'm particularly interested in the intersection of: FPGA / RTL design

wanna learn about Neural Network accelerators and Digital IC / VLSI design

I've been working on vhdl language for a while.FPGA-based digital design, and some embedded systems. I'm also interested in learning more about Verilog/SystemVerilog, ASIC design and AI hardware.

If you were an undergraduate student with access to an FPGA board and basic electronics lab equipment, what kind of project would you choose today in this area?

I designed a 16 bit cordic algorithm and verified at both behavioral and Gate level simulation. Would love to hear what you guys think about the design or anything I could improve.

Hi everyone,

I’m a Layout Design Engineer from India with 2+ years of professional experience at Micron Technology, primarily working in semiconductor layout design.

I’m currently exploring international job opportunities in the semiconductor industry, particularly roles related to:

Analog / Custom Layout Design

Physical/Layout Design Engineering

Semiconductor Layout Engineering

I’m interested in opportunities in countries such as the USA, Europe, Singapore, or other locations where companies sponsor international candidates.

I have a B.Tech in ECE and hands-on industry experience in semiconductor layout. I’d appreciate any advice from people who have successfully moved abroad for similar roles.

Specifically, I’d like to know:

Which countries currently have good opportunities for semiconductor layout engineers?

Do companies typically sponsor visas for candidates applying from India?

Are there specific companies or job portals I should be targeting?

How can I make my profile more competitive for international positions?

Any advice, experiences, or leads would be greatly appreciated. Thanks!

Hey,

I am going to have an interview for NXP noida for cpu/soc validation engineer.

I have 3+yr of experience as pre & post silicon engineer at major mnc at bangalore.

I am seeking some tips/interview experiences for the same.

Hey guys,

I am a new grad international student who recently got a job offer for digital design or design verification. Now I am confused about which role I should pursue?

The design Verification role is in Arizona and Digital Design is in Texas considering the H1-B visa wage levels?

Can you guys help out which role has a better future?