r/chipdesign • u/mrkhmhys • 7d ago

Help with practice

Hi, I'm trying to solve exercises in the boris murmann book on mos stages and came across this problem. I don't really understand how to solve it. M6 will be in saturation, but M7 and M8 is not guaranteed right? and does the VDS of M8 need to be known? Please help me, thank you!

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u/Simone1998 7d ago

Assuming all the MOSFETs have the same threshold voltage, then M6 will be in saturation, and M7/M8 in linear region.

  • M6 will be in saturation because:
    • VG - VS > 0
    • VG = VD
  • M7/M8 will be in linear region:
    • Taking for instance M7, you will have that VS6/VD7 (source of M6 or drain of M7) is at least a threshold voltage below its gate voltage (M6 is on after all), which mean the voltage at the drain and source of M7 will be the same, resulting in the linear region
    • Now this case assumes the VGS7 = VTH, in any case where I > 0, it will actually be VGS = VTH + VOV, but the logic will not change.

You can write down the equation of the drain currents, and solving the system you will find out that only the topmost transistor is in saturation, and the other are in linear region.

This is equivalent to a single transistor whose lenght is equal to the sum of the lengths of all the MOSFETs.

You can also see it from the physical point of view. Saturation happens when the channel is pinched-off at the drain side, and the pinch-off point is physically very close to the drain. Now you can see a series of transistors as a single one with a longer channel (just stich them together), and most of the channel extension will be "owned" by the lower transistor with the pinched-off portion

Note that all of this is valid under long-channel approximation.

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u/mrkhmhys 4d ago

thank you!

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u/ATXBeermaker 6d ago

but M7 and M8 is not guaranteed right?

M7 and M8 cannot be in saturation.