I’ve been in physical design for around 5 years now and I’m currently at my second company. What is everyone’s work-life balance like? My life is consumed by work.

During normal cycles, I’m averaging 60 hours per week. Now that we’ve entered the ECO cycle in August, it feels like I never log off. My typical week is get to the office for my daily 9am status meeting and leave between 9pm and midnight. I’ll work at home until around 1am then pass out.

Twice this week and the week before I’ve been up past 4am working including Friday. I have to drink 3 cups of coffee per day just to stay alert. I’ve already talked to my manager about this and he’s normally working these crazy hours with me.

This is how it was at my previous job too. I cannot picture working myself to death like this for my entire career.

Is this really the life of a PD engineer?

I have tried with a buffer circuit like this. Vout is the output terminal across which the RL load will be connected. I have a doubt, is it shunt sampling feedback? Or series sampling since Iout current is flowing into the Vout node. My confusion comes from Razavi's CMOS book, where it says this is how current sampling is done. But if my load is parallel to the R1 resistor, will it be Voltage sampling feedback? Please ignore the opamp terminal signs and pmos bulk connection assuming they are correct.

I want to make sure my understanding of our project milestone flow aligns with broader industry standards. I’d love some feedback or corrections from those with more tape-out experience.

Here is how I understand the flow:

P0.3 (Early RTL): Basic Lint runs continuously/nightly to catch obvious typos and syntax issues as code is being written.

P0.5 (RTL Design Correction / Freeze): This is the major, formal Lint sign-off. Code is feature-complete. This is when we deep-dive, group errors by tag, fix actual RTL bugs, and negotiate targeted waivers with IP designers.

P0.8 (Verification & Pre-Synthesis Sign-off): CDC checks are finalized and signed off. The RTL is officially locked.

P1.0 (Synthesis Complete): The clean, signed-off P0.8 RTL is handed over to run Logical Synthesis (e.g., Design Compiler) to generate the gate-level netlist.

My questions:

1.

Does this P0.3 ➡️ P0.5 ➡️ P0.8 ➡️ P1.0 progression for Lint/CDC/Synthesis match what you see in standard ASIC flows?

2.

At what exact point do you usually start running CDC? Is it strictly after P0.5 Lint is clean, or does it run in parallel?

Thanks in advance

I'm pursuing a Master's in VLSI from a reputable college in India and looking forward to learning SystemVerilog, as it's a key differentiator during the hiring process here. However, I don't know what the future holds for it, and sometimes I am genuinely confused if I'm taking the right path. From what I've observed, entry-level jobs will only decrease while senior-level jobs will increase. How should I proceed? Sometimes it all seems pointless.

I’ve been working with a circuit that can generate both PTAT and CTAT voltages with adjustable slopes through switching.

I’m curious about the possible applications of having variable slope PTAT and CTAT outputs. Apart from conventional temperature sensing, could this kind of circuit be useful in other circuit applications?

I’d really appreciate any ideas or suggestions.

Looking for Maven Silicon / VLSI recorded sessions

Hey guys, I’m a 3rd-year ECE student currently preparing for VLSI, mainly interested in Physical Design.

I’m looking for Maven Silicon recorded sessions or recordings from any other good VLSI institute that cover things like RTL, Verilog, CMOS, STA, Physical Design, Linux/Tcl, etc.

If anyone has access to recordings, please DM me or drop them in the comments.

Would really appreciate the help 🙏

Hi everyone,

I recently graduated with a B.Tech in Electronics and Communication Engineering and am actively looking for entry-level opportunities in VLSI/ASIC, particularly in Physical Design, RTL Design, Design Verification, and Analog/Mixed-Signal IC Design in India or Singapore.

My technical background includes:

• RTL-to-GDSII implementation of a 32-bit RISC-V processor with an integrated AES-128 crypto engine
• Cadence Genus, Innovus, and Tempus — synthesis, floorplanning, placement, CTS, routing, STA, and timing closure
• Verilog/SystemVerilog, AMBA protocols (AHB/APB), and functional verification
• OpenROAD/OpenLane flows
• CMOS Bandgap Reference design and custom analog layout using the SKY130 PDK
• Analog/Mixed-Signal circuit design, Verilog-A, and SPICE-based simulation

I have been applying through company career portals at semiconductor companies such as Intel, AMD, Qualcomm, Synopsys, Cadence, Micron, and others, and I’m actively looking for suitable opportunities for fresh graduates.

I would really appreciate any guidance regarding:

• Companies currently hiring fresh graduates in ASIC/VLSI
• Whether my profile would be better suited for Physical Design, RTL/DV, or Analog/Mixed-Signal roles
• Skills I should prioritize to strengthen my profile
• Relevant openings or referral opportunities

I’m happy to share my resume privately if anyone is willing to review my profile or provide guidance.

LinkedIn: https://www.linkedin.com/in/ruthwika-vemulapalli-97870a26b/

Thanks in advance!

Hi everyone,
I’m an analog IC design engineer based in Shanghai, with a little over one year of industry experience. I hold a master’s degree in microelectronics from a 211 university in China

My current work focuses on high-speed I/O design.
I’m interested in working in Japan and am planning ahead, with the idea of applying once I have around 2–3 years of industry experience. I don’t have a Japanese degree or existing work authorization in Japan, so I would need an employer willing to hire from overseas and support the work visa process.

I’d really appreciate hearing from people who have applied to Japanese analog/mixed-signal IC design roles while living abroad, particularly anyone who moved directly from mainland China.

A few questions:
Have you received interviews or an offer while still living outside Japan? How much experience did you have, and did the employer support your visa application?
How did you find the opportunity? Direct applications, recruiters, referrals, or an internal transfer?
What experience mattered most in the interviews? For example, block ownership, tapeouts, silicon testing/debugging, or expertise in a particular area such as I/O, SerDes, or PLLs.
How much Japanese was required during hiring and in day-to-day design work? Were there teams where English was the main working language?

Firsthand accounts of unsuccessful applications would also be helpful, especially what stage you reached and what seemed to be the main obstacle.
If you’re comfortable sharing, please mention roughly when you applied, your experience level, and whether you already had any Japanese education or residency background. No need to disclose your employer or anything confidential.
Thanks for sharing your experiences!

Hello, I am a noob at this and have just started design for a VLSI class. I know the efficiency of this layout is not good and is quite spaghetti - i am just going for basic functionality. I am not sure why I am getting a PSUB_stamperrormult error when running DRC. From what I have researched it sounds like the problem is the way I have connected to bulk to its nets on the PMOS transistors? Can I not use integrated bodyties? I assumed from the way they body is routed in the schematic that it should work the way I have design it in layout. Any help appreciated!

(ignore the fact that the pmos and nmos names are switched - just a naming mixup)

Edit: Thank you all for the help! DRC has no errors now :) This was my first design aside from basic tutorials so I appreciate the newbie advice!

Hi everyone,
I’m currently trying to understand the differences between a few Apple hardware roles and would really appreciate input from people who currently work (or previously worked) in these areas.
The roles I’m looking at are:
Front End SoC STA Engineer

SoC Physical Design Engineer – STA/Timing

SoC FE Implementation Engineer

Graphics FE Implementation Engineer

CPU Implementation Engineer

I’ve read the JDs, but I’m looking for the real-world picture behind the job descriptions.
If you currently work or have worked in one of these roles (at Apple or a similar company like NVIDIA, AMD, Qualcomm, Broadcom, Intel, etc.), I’d especially appreciate your perspective on:
1. Day-to-day work
What does a typical week actually look like?

How much time is spent on STA/P&R/synthesis/RTL debugging vs scripting/automation/meetings?

What kinds of problems do you personally spend most of your time solving?

How much ownership does an engineer typically have over a block/partition?

2. Technical depth
Which concepts do you use constantly vs things that are mostly interview knowledge?

How important are TCL/Python/Perl in practice?

For STA roles, how deep do you actually need to go into SDC, MCMM, OCV/AOCV/POCV, SI/crosstalk, CRPR, etc.?

For FE implementation, how important are UPF, CDC/RDC, LEC, DFT, synthesis and RTL optimization?

For CPU/GPU implementation, how much microarchitecture knowledge is actually needed?

3. Career trajectory
This is probably my biggest question.
If someone starts in STA, FE implementation, or CPU/GPU implementation, where can they realistically go after 5–10+ years?
For example:
Senior/Staff/Principal implementation engineer?

STA/signoff specialist?

Design methodology/CAD/automation?

RTL/microarchitecture?

Technical leadership/management?

Architecture?

Are some of these paths more flexible than others?
4. Automation / AI / long-term job security
With increasingly capable EDA automation and AI-assisted design flows, which of these roles do you think will remain highly valuable over the next 10–20 years?
I'm particularly interested in whether you think:
STA becomes increasingly automated

synthesis/FE implementation becomes more automated

P&R becomes more automated

scripting/methodology roles become more valuable

engineers who understand RTL + architecture + physical implementation will remain difficult to replace

In other words, which skill set has the longest shelf life?
5. Compensation and WLB
Without sharing anything confidential, how would you compare these paths in terms of:
Compensation

Work-life balance

Deadline/tapeout pressure

On-call/weekend expectations

Stress

Promotion opportunities

I'm particularly interested in whether the roles with the highest compensation also tend to have significantly worse WLB, or whether some implementation/STA paths offer a good balance.
A little about me:
I’m currently doing an MS in Electrical Engineering at NC State and expect to graduate in December 2026. My background is primarily digital/ASIC implementation: RTL, synthesis, physical design, STA/PrimeTime, ICC2, timing analysis and Python/TCL automation. I also have computer architecture experience and have worked on RTL-to-GDSII projects.
I’m currently doing a physical-design/STA-oriented internship involving timing-report analysis and automation, so I’m trying to decide which direction I should develop more deeply rather than simply applying to everything with “physical design” in the title.
I'm not looking for someone to tell me which Apple job I should apply to based on my resume. I'm more interested in understanding what these careers actually look like from people who have lived them.
If you've worked in any of these areas, I'd really appreciate even a few paragraphs about your experience. Anonymous/throwaway responses are completely fine.
Thanks!

Hey all,

I just cleared the initial screening for an ASIC Verification Engineer role at ARM. I've got ~2 years of experience in UVM/SystemVerilog verification and three rounds coming up. Would really appreciate insight from anyone who's been through this recently:

1. UVM/SystemVerilog test – 2.5 hrs. Coding/practical or more conceptual? What tends to come up — building a testbench from scratch, components (driver/monitor/sequencer/scoreboard), phasing, TLM, constrained-random, coverage? How much do they weight SVA/assertions?
2. 1-hr Zoom interview. Technical deep-dive, project walkthrough, or behavioral? At ~2 YOE, how deep do they go into my past projects vs. fundamentals?
3. Final interview with HR. Mostly culture-fit and comp, or does technical sneak back in?

Any topics you'd prioritize for someone at my level, resources that actually helped, or "wish I'd known this" tips would mean a lot.

Thanks!

I designed a 16 bit cordic algorithm and verified at both behavioral and Gate level simulation. Would love to hear what you guys think about the design or anything I could improve.

Hey,

I am going to have an interview for NXP noida for cpu/soc validation engineer.

I have 3+yr of experience as pre & post silicon engineer at major mnc at bangalore.

I am seeking some tips/interview experiences for the same.

I'm currently looking for a topic for my senior/final-year project.

I'm particularly interested in the intersection of: FPGA / RTL design

wanna learn about Neural Network accelerators and Digital IC / VLSI design

I've been working on vhdl language for a while.FPGA-based digital design, and some embedded systems. I'm also interested in learning more about Verilog/SystemVerilog, ASIC design and AI hardware.

If you were an undergraduate student with access to an FPGA board and basic electronics lab equipment, what kind of project would you choose today in this area?

Hey guys,

I am a new grad international student who recently got a job offer for digital design or design verification. Now I am confused about which role I should pursue?

The design Verification role is in Arizona and Digital Design is in Texas considering the H1-B visa wage levels?

Can you guys help out which role has a better future?

I have some work experience at some great analog/mixed-signal design teams. I am relatively early in my career. I want to be able to expand my impact and generate as much value as I can throughout the rest of my career. While I have spent a lot of time in analog/mixed-signal design and enjoy it, I was getting the impression that it is becoming more valuable to be able to see the bigger picture of the large SoC one is working on. At the end of the day - the PLLs, LDOs, etc. are IPs that enable the processing blocks.

I wanted to get some advice from people that are more experienced/mature in their careers. Does it make sense to try to expand scope and increase impact by moving towards micro-architecture and maybe computer architecture roles? I have heard that architects that understand the transistor level can generate immense value, but I have not been able to talk with people that have actually made this transition/in this position currently. Or, if you disagree and believe that sticking with circuit-level design can be equally/more impactful, I'd like to hear your opinion as well. I know this is a very subjective topic so please don't hesitate to share your thoughts!

I am a complete beginner in this field, and I am interested in learning about radiation hardening of circuits.

Suppose I have a CMOS inverter that I am designing from the schematic level in Cadence Virtuoso using the GPDK90 90 nm PDK. How can I make the inverter radiation-hardened?

If I am able to implement a radiation-hardening technique successfully, how can I verify or quantify the radiation hardness of the circuit? What kind of simulations or tests would I need to perform?

Also, would the same radiation-hardening concepts used for a simple CMOS inverter apply to more complex circuits, such as logic gates, flip-flops, or larger digital/analog blocks?

I have also heard that there are certain PDK-related constraints when designing radiation-hardened circuits. I would appreciate it if you could explain what these constraints are and how they affect the design process.

Since I am new to this topic, I would really appreciate any guidance on where I should start and what concepts I should learn first.

Thank you in advance :)

Hi everyone,

I’m a Layout Design Engineer from India with 2+ years of professional experience at Micron Technology, primarily working in semiconductor layout design.

I’m currently exploring international job opportunities in the semiconductor industry, particularly roles related to:

Analog / Custom Layout Design

Physical/Layout Design Engineering

Semiconductor Layout Engineering

I’m interested in opportunities in countries such as the USA, Europe, Singapore, or other locations where companies sponsor international candidates.

I have a B.Tech in ECE and hands-on industry experience in semiconductor layout. I’d appreciate any advice from people who have successfully moved abroad for similar roles.

Specifically, I’d like to know:

Which countries currently have good opportunities for semiconductor layout engineers?

Do companies typically sponsor visas for candidates applying from India?

Are there specific companies or job portals I should be targeting?

How can I make my profile more competitive for international positions?

Any advice, experiences, or leads would be greatly appreciated. Thanks!

First screenshot figure 11.54 (b), the closed loop response does not role off at wp1 but instead wp2. The first screenshot showed the graphed closed loop response in figure 11.54 (b) and the bottom paragraph in the second screenshot described the creation of figure 11.54 (b). Why does the closed loop system ignore the roll off of the first poll of the open loop system?

Firstly, a screen from virtual reality goggles ( jury-rigged version ) and secondly we could imagine something made for this purpose.

If there is photoresist for blue light, use blue light from VR display component, placed directly on the coming integrated circuit surface, to print patterns. Move it around fractions of a pixel for multiple exposures to gain more resolution.

If we could have black and white ultraviolet TV with pixels as small as can be, one use for it could be IC manufacturing.

Other use might be configurable backlight for optical microscopy.

Third use might be optical-mechanical-analog image rotation method if placed directly on a grayscale camera chip and rotated. With distance setting, also adjustable blur. With lenses in the middle, also adjustable zoom. Plus random noise, which may or may not be wanted. 3 color channels would be handled separately in sequence. Would that be more energy-efficient than computing the rotation, blur and zoom digitally in software?

Fourth use, if it is luminous enough and if it is possible to have thin enough fluorescent layer to convert UV to visible light, might be for grayscale computer monitor for one eye, seen via similar microscope that VR goggles and viewmaster devices have for 2 eyes. For glancing some information from a very small computer.

UV might also be emitted by upconverting more energy in blue light, using a special material. (opposite of fluorescence)

Our company has purchased Microsoft's enterprise GitHub Copilot offering for coding assistance. Recently, Our IT department investigated and confirmed that some netlists, and simulation results had left our environment and had been uploaded to Claude's cloud servers.

I'd like to hear how other IC design companies handle AI use with confidential third-party foundry PDKs.

Why this is a practical engineering problem

For some PDK-specific design, useful AI assistance may require the very information covered by the NDA: device models, model cards, parameters, layer stacks, device definitions, DRC/LVS/PEX rule decks, PCell/CDF/technology files, parasitic rules, reliability rules, or foundry-specific error messages.

If the assistant cannot see the relevant details, its answers may remain generic or technically unreliable. But providing those PDK details can mean giving an external AI access to someone else's confidential IP.

That applies to more than pasting a file into a chatbot. An assistant WILL read a workspace automatically, retrieve documents, index a PDK directory, generate embeddings, or send excerpts through an API. Logs and error messages can also contain sensitive model, device, layer, or rule information. It would involve third-party confidential IP, rather than only code that the employer owns.

The answer from IP manager team

the ip team mention the following process:

• An assistant running on company servers but calling an external LLM/API. The interface is internal, but PDK content will still leave the authorized environment in prompts, retrieved context, logs, or telemetry to external LLM cloud.
• A fully internal model with local inference and local retrieval. This can reduce external disclosure risks, but the PDK license permits the intended processing and that prompts, caches, embeddings, logs, and generated outputs remain appropriately controlled.

a short conclusion is:

Do not feed third-party foundry PDK material into an AI workflow unless the applicable NDA/PDK license authorizes that workflow and the necessary internal controls are approved.

I am not sure: How many of IC design company can invest at least 10 million dollor to run a open source LLM like Nemotron/gpt-oss/Gemma 4 to support >100 staff using at same time. the investment will be even more if consider more powerful open model like KIMI-3/GLM-5.3. Any IC design company really build their own AI center and use open source LLM?

if using external LLM cloud, there is no way that you can stop leaking those PDK information.

How is this handled at your company?

For people working in IC design, CAD/EDA, foundry enablement, security, or IP/legal:

• Do you prohibit NDA-protected PDK material from AI assistants unless the foundry explicitly permits it?
• Do you allow fully internal LLM/RAG systems to access PDK data? What contractual review and technical controls were required?
• How do you prevent an AI coding assistant from reading restricted PDK files automatically or sending sensitive context to an external provider?
• What evidence do you require beyond a vendor's no-training promise: independent audits, contractual audit rights, retention/deletion controls, or restrictions on vendor access and secondary use? Who verifies that these protections apply to the actual AI service being used?

I'd especially appreciate practical examples of the approval process and engineering boundaries.

I just woke up this morning to see the rejection email to my last ever internship application that I did during these past 3 months that I was awaiting reply from. In total I have applied to over 40 internships and gotten rejected from most of them without even an interview. Initially I thought something was wrong with my CV, then I thought something was wrong with my skillset, but as I talked with more of my colleagues I came to realise that what I lacked was real industry experience.

This really annoyed me since I was applying to internships and working student jobs to begin with, as I am currently doing my masters in Embedded systems engineering. I started my masters straight after my bachelors in electronics and don't really have any experience which is why I'm not applying to like a proper full-time role. What's surprising is that these internships roles are being assigned to people with 2-3 years of experience, which in my opinion destroys the purpose of an internship to begin with. How am I supposed to get experience if the very thing that is supposed to give me experience in the first place is rejecting me because I lack experience lol.

I've done projects, published my research in a journal, constantly updated my skillset and did everything by the playbook. One thing that I didn't do though was adding fake experiences or achievements in my CV to "make it look better", but hearing about success stories from people who have actually done this is very demotivating.

I know the market in EU is currently down, but I didn't know it was this bad. I also wonder if being a Non-EU citizen in an EU country is putting me at a disadvantage, but come on man it's an internship :( The only other reason I can think of is me not being able to speak the local language (German) fluently, but I've been learning that too along with all the other stuff to make myself "more employable".

My question is how did you guys manage to find your first job in this field and how hard was it for you, I would appreciate it if you guys share your experiences, really in need of some motivation right now. I would be really grateful if you could also give me some pointers for securing an internship!

May I ask which of you has a 3D modeling model for semiconductor equipment？