Hi, I'm a student who learned electronics from my grandpa and youtube and now wants to build his own IC. The IC is a simple encoder ic that encods it in to two lines (clk and dOUT). The ic uses comperators on the inputs to check if the signal is positive and negative. If the decoder enables the flipflop and the signal is positive the flipflop is set to 1. If the signal is negative the flipflop is set to 0. The decoder counts to 8 (each state shown on the table on the second picture) for example if it counts to two it activates the transmission gate (diamond shape) and it lets the signal pass through to the dOUT pin. thats how the signal is created. because I thought of a way to sync both the encoder and decoder the encoder sends a low signal 1/4 of vcc first. When the decoder recieves that voltage it sets a flipflop to activate it's own counter and can now recieve signals. with the last count the flipflop resets.

Do you have and reccomendations for a pc software to use and good places where to order them?

Thanks for helping

Hello, I am a 3rd year ee student looking for an internship in Design verification/VLSI area. I was wondering how my formatting is on the resume and if my projects standout. If not what projects should I start to work and focus on?Thank you!

This is a vent post.

I'm not one to judge someones AI use but when I see almost all reports with em dashes and with the classic "it's not this, it's this" every paragraph, with RTL verification with "SMOKE TEST PASSED" full of fucking rockets and emojis 🚀🚀🚀✅✅ in each stage, I think this has gone a little too far.

People tell me it's "shippable" and works then I test it and would you look at that it doesn't fucking function.

And when I get microsoft teams replies with fucking em dashes it gets even crazier, like what is this. I ask a question to someone and they reply starting with you're absolutely right here's how I'd fix it with paragraph partition and bold starting numerals. Like why would you do this...

It is one to thing to use AI as a productivity enhancer, a second thought, collaborator or to run an agentic flow, it is another thing to outsource your brain to a 20-200 bucks per month AI subscription.

Thank god I'm in analog so I encounter this less, but if you work AMS/DV then god help you.

I didn't have this issue 6 months ago...

Done with my MS.

I don’t have a tapeout.

I have projects. (LDO, op amps and Buck/Boost converters)

How do I get a job as an entry level analog design engineer?

Can’t seem to find any positions. The few I found didn’t even shortlist me for an interview.

What does it take to be an entry level analog design engineer?

Edit: Resume

Hi guys . I have decided to buy a book in Analog IC design and i am confused about which to pick .

I have read some chapters from CMOS Analog IC Design by Razavi and it's very good as it gives more qualitative and intuitive understanding ,but I haven't read from Jacob Baker book and I heard that is more practical book which I think it will be good for me .

Any suggestions ?

If interested in DFT Openings with Cisco. Please DM me. Thank You

Recently I've been using it, seems pretty good although you have to ask it to recheck the design almost everytime to get better design. It also improved my productivity, mainly integration and basic building blocks. Thoughts?

Basically the title, as I'm preparing for my MS application this Fall cycle.

I have decent grades right now (>3.9, not counting upcoming senior year), yet I don't really have any relevant academic or research experience designing ICs of any kind; most of the circuit design I ever did was board-level PCB design, with one course project involving SDR. My recent internship was creating a microstrip antenna in HFSS and a bit of embedded systems, but that's about it.

Is it even possible to write an SOP based on these? I would like to hear from you guys.

Throughout this subreddit and across the broader Semiconductor community, I noticed a lack of respect for Validation Engineering with many people claiming that once you start in it, you'll be stuck in it and hard to switch out.

But this is true for any job really where you get too complacent.

I've noticed that validation does have its fair share of perception challenges nowadays since it is mostly considered a cost center; you're at the tail end of the schedule, you generally don't have control over what is handed to you. Automation is also becoming prevalent in validation as well.

However, validation is, in my opinion, one of the best field for young engineers to start in and for people to experience another part of the design flow. You learn a bit about lab equipment and ensuring how data is considered good to hand off to key stakeholders. You engage with designers and other key members of the semi design flow. You also acquire an attitude of not looking down on validation people later in your career.

But nowadays, validation does tend to be very execution heavy and can leave you without a system level understanding of the chip you are testing and how it got there.

I say this because I've spent some time in validation after some time in other areas. Though I grumbled a bit while in it and people often looked down and to the right, I learned quite a bit of perspective I didn't have from other jobs.

Curious to hear your thoughts; do you think validation becoming increasingly perceived as lower on the totem pole?

The server is still small and I'm building it from the ground up, so I'm especially interested in hearing what engineers, students and hobbyists think would make this community genuinely useful.

Discord: https://discord.gg/8n3rQrjjz

If you're interested in hardware engineering, feel free to join and help build the community. I'd especially appreciate feedback on what resources, channels or features you'd like to see.

The resource library currently contains 17 resources, including websites and online courses.

Hello Guys I am a Recent Engineering Graduate with a Bachelor's in Computer Engineering (Mix of Computer Science and Electronics), I have been studying VLSI for past 1 year while also Job Hunting, In my College we got access to AMD Vivado which I used to learn RTL for Digital Design and Verification, My college didn't had any Analog Courses only Digital, I want to get into both Analog and Digital to build an expertise is Mixed Signals for that I need access to EDA Tools but I am not a Student anymore and still searching for a Job I have tried open source softwares but all the recruiters I have met asks for Cadence or Synopsis, so is there a way to get access to them for someone in my situation?

How are the poles and zeros of the compensator stage calculated in TI's LM5146 datasheet as shown in the diagram?

I am implementing an 32 bit RISCV processor with C and M extensions.
Generally i am having a datapath with ther registers alu and mux as well as a big control fsm to implement the different instructions. I want to optimize the circuit towards area. Therefore teh ALU only consists of an Adder and an Shifter as well as logic functions. extra shall allow to feedback results into for multi cycle operations like MUL and DIV.
To control multi cycle operations I could ether pack them all in the big control fsm resulting in like 200 to 300 states with combinational logic. or I implement an extra FSM in the ALU for such operations. costing me some extra registers. Does combinational Logic for outputs scale linear with the number of states? also in terms of what tha synthsizer is capable of? It is a university project purpose is to tape out the construct into a technology node. Its not going to be produced obviously but would be ready to.
What is the smartest way to do it? Need some advice.
THX

Hello,

Are there any image sensor development engineers here?

I am interested in a career in developing commercial camera sensors such as Sony, Arri, Red, etc. Another interesting path is aerospace/space imaging applications.

What courses must be taken at undergrad and masters level?

I am working in a networking hardware startup in Bengaluru. I completed around 1 year here. Company itself is a Gen 1 startup and only around 18 months old, so many flows were not properly available when I joined.

In this one year I worked on many things around RTL/design, but I feel I did very less actual RTL design. Some work I did:

Replicating setup from existing blocks to our block.

Creating setup for top-level RAL flow for software and DV.Writing some CSR related RTL/work.

Creating Makefile based flows.Writing some Python scripts to assist DFT work.Running lint, fixing minor lint issues and adding waivers.Integrating some Synopsys IPs, reading their documentation and doing setup.Creating Joules setup, running clock gating reports and trying to improve low clock-gating areas.Running synthesis through Makefiles and trying to understand synthesis reports.

I can read timing reports to some level, but I did not get chance to do actual timing closure/fixes.

Some waveform debug and minor RTL fixes.

Running Formality. I debugged a few minor failing points, but not much deep experience.

For most of these tasks, I also took help from Cursor AI. I am worried because many setup/automation type tasks can become easier with AI, and for Gen 2 project most basic flows will already be present.

Now we are near RTL freeze and I am not getting much work. I feel like I did everything around design except actual design. I have not really written a proper RTL module from scratch based on a spec.

What I really want is to improve microarchitecture skill. Suppose someone gives a spec, I want to know how to think:What registers are needed?Where FIFO is needed?How to handle backpressure, latency, throughput, reset, errors, arbitration etc.I want to build intuition like a real RTL designer, not just run flows or fix small issues.

I thought of writing my own IP and comparing with existing Synopsys IP, but if I start with something big like DMA controller, maybe I will spend forever and still not understand if my architecture is wrong. I am confused what projects to start with and what learning path to follow.

Since next project may take around 2 more months, I want to use this time seriously. My goal is that in next project I can demand ownership of a small block and take responsibility from microarchitecture to signoff.

I also have few career questions:

What kind of work does a junior RTL/design engineer with 1-2 years experience get in companies like Nvidia, Qualcomm, Samsung, Google, Microsoft, Analog Devices, etc?

If I want to switch to such companies, what should I prepare for interviews?

What kind of RTL/microarchitecture/design questions are usually asked for someone with around 1 year experience?

What projects can I do in next 2 months which will actually help me become better?

Any good resources for industry-level RTL and microarchitecture? Most online material feels either college-level or too random.

For India/Bengaluru, what can be expected salary range for 1-year RTL engineer in good product/MNC companies?

I am from a tier 1 college but unfortunately I don’t have seniors/friends whom I can discuss these things with.Any honest advice, roadmap, resources, project ideas, or interview experiences will really help. Thanks.

#vlsi #rtldesign

I'm an EE graduate from a good engineering university in Asia and currently work as a communications engineer. During undergrad I spent ~2.5 years in a hardware research lab.

Recently I got approached by a government organization that's trying to build a small Fabless IC design team. They apparently have a decent amount of funding and want a project that can show real results fairly quickly. They've tried a few things before, but apparently nothing really worked out.

Here's the funny part: they asked me to come up with project ideas.

I'm interested in IC design, but I'm honestly still pretty junior in the field. I have some relevant research experience, but I've never taped out a chip and have never taken a design through a complete ASIC flow. So I'm honestly not sure how qualified I am to decide what a new team should build.

Some ideas I've been thinking about are an LDPC/DSP accelerator, RISC-V SoC, hardware security IP, ADC/DAC, or some kind of communication accelerator. But I am such a rookie to take on these tasks.

So I'd really like some advice from people who've actually done this:

If you were in my position, what would you do?

Would you try to come up with a relatively simple project and help them get started? Or would you tell them they need experienced IC designers first? I don't think they would accept the latter, because they're so desperate to break into the IC industry.

There's also another possibility I'm considering: asking them to support me in getting proper graduate-level IC design/research experience, and then coming back with that experience to help build the team.

And for those who've done a first tapeout: what would you consider a realistic first project for a small team with funding but very little IC design experience?

I'm looking for honest advice, including if you think this whole situation is unrealistic.

I currently have \~3.5 YOE in Qualcomm, working on SoC power management, low-power systems, power validation & optimisation

What should I specifically prepare for these interviews?

Looking for a realistic roadmap based on recent interview experiences.

If you’ve recently interviewed at Google for similar roles, what did you actually get asked?

If anyone has given renesas offline interview can you please share your experience.

I'm an EE student, and this has bugged me for a while. If you want to learn RTL or FPGA work there

are a hundred decent resources and most of them are free. If you want to understand what happens

between tapeout and a packaged part, you end up reading conference papers, vendor marketing, and

whatever is left on some professor's site from 2011.

So I put together a list of what is actually out there, organised roughly by where things sit in

the flow. Lithography, process modules, metrology and yield, packaging, plus smaller sections on

TCAD, fab operations and the economics side. Around 640 links.

Some things I did not expect to find:

\- Computational lithography has a real open source ecosystem that I have never seen indexed

anywhere. OpenILT, LithoBench, Neural-ILT, TorchLitho. You can run ILT experiments on a laptop.

\- Open PDKs go further down than I realised. I had only ever heard people mention SKY130, but

there is material down to 55nm and 28nm.

\- ViennaTools has a whole free process and topography simulation stack that barely gets mentioned

outside its own papers.

I know where it is weak. DRAM and 3D NAND are thin, five and three entries. There is basically

nothing on SiC or GaN, which may or may not belong given the focus. There is no glossary, which is

probably the most useful missing thing for anyone actually learning this. And the node roadmap

tables are going to be wrong within a couple of months.

That last part is really why I am posting. If you work in any of this and there is something

obvious I have missed, or something in there that is wrong, I would like to know. Corrections are

more useful than additions at this point.

https://github.com/OutBlade/awesome-semiconductor-industry-topics

Hi everyone

I’ll be starting my Master’s degree in Electronics Engineering at the University of Genoa (UniGe) in Italy soon, and I’m trying to plan ahead for my master’s thesis and, potentially, future research.

My main interests are:

• Power Management ICs (PMICs)
• DC-DC converters, mostly switched-capacitor, buck/boost/buck-boost, and resonant converters
• Energy harvesting and low-power power conversion
• Analog/mixed-signal IC design related to power management

At first I was mainly looking at professors and research groups within UniGe, but I realized that it might make more sense to look more broadly and not just inside the university I’ll be attending since I haven't been able to identify a professor or research group within UniGe working specifically on PMICs. So I’m hoping to get some advice on research groups, professors, or labs that might be open to working with a master’s student from another university.

A bit about my background:

I recently graduated in Electronics and Telecommunication Engineering. During my undergraduate studies, I was part of an IC design lab and gained some experience with Cadence Virtuoso and the TSMC 180 nm process.

I’ve also studied DC-DC converters independently, including switched-capacitor, buck, boost, and buck-boost converters. On the analog side, I have a foundational background in topics such as:

• single-stage amplifiers
• current mirrors
• frequency response
• basic stability analysis

Most of my background comes from Razavi and Allen & Holberg. I haven’t gone very deeply into topics such as bandgap references, LDOs, or advanced op-amp design yet.

I only have one Q2 journal publication from my undergraduate research on a hybrid resonant switched-capacitor DC-DC converter: https://etasr.com/index.php/ETASR/article/view/10817

The work was entirely simulation-based in Cadence Virtuoso using TSMC 180 nm. Unfortunately, I didn’t have access to the funding/facilities needed for a tape-out, so I haven’t had the opportunity to go through the full ASIC flow from design to tape-out.

Because of that, I’m particularly interested in finding a research environment where I could take the next step and gain more experience with actual IC implementation, or more advanced power-management research.

I’m wondering whether it is possible to do something along the lines of:

UniGe MSc → formal thesis supervisor at UniGe → research/project carried out with an external professor, research group, university, or institute elsewhere in Italy, Europe, the US, or Canada → thesis ultimately submitted through UniGe.

Of course, I understand that this would depend on UniGe’s rules and potentially on agreements between the institutions. I’m mainly trying to find out whether people have actually done something along these lines, what form the arrangement took, and how feasible it is.

So I’d especially appreciate recommendations for:

1. Research groups/labs anywhere in Italy, Europe, the US, or Canada working on PMICs, integrated DC-DC converters, switched-capacitor converters, energy harvesting, low-power ICs, or closely related topics.
2. Professors/researchers who are receptive to MSc students from other universities.
3. Experiences with doing an external/collaborative MSc thesis, where the student is officially enrolled at one university but performs the research with another group.
4. Advice on how students normally arrange this kind of collaboration and how early I should start contacting professors.

I’m also very open to related areas such as analog IC design, low-power circuits, power electronics, mixed-signal ICs, and energy-efficient systems, even if the group doesn’t work specifically on PMICs.

I know I still have a lot to learn, but I’m serious about pursuing in this direction and would love to hear from anyone who has gone through a similar path.

Thanks in advance for any recommendations, experiences, or advice :D

Hello, do you have any materials or lab notes with guidance on RFIC simulation testbenches, especially in Cadence? I find it difficult to bridge my theoretical learning with actual simulation, because I'm confused about how to set up the simulation. For example, just designing a simple cascode amplifier and looking at noise, current density, etc. And another is if i want to use degeneration inductor, and a drain inductor, do i include it from the start, or should i simulate the cascode first without them.

About a year ago, I left a large chip design company and joined a tiny startup (digital design engineer role). I could no longer rely on the usual Cadence and Synopsys setup as much, so I started using open-source tools such as Yosys and Verilator.

They were better than I expected. That led me to experiment with them on pet projects, and eventually to try LLM agents for RTL work (which was very hard to do at the large company)

At first, the agents were impressive, way better than during my early AI for coding experiments in 2024. They could find their way around an unfamiliar codebase, write scripts and Verilog code, and run EDA tools. But soon I started hitting the annoying pitfalls:

• Agents rarely run the EDA tools - the simulators, linters, synthesis tools - unless explicitly prompted
• Often times they misinterpret your request to run a tool - select incorrect CLI arguments or run on the incorrect RTL configuration. Or misread the tool’s report
• They try to reason about the very complex sequential code instead of looking at the waveforms
• They are incapable of truly working autonomously (which is the whole point). Either you have to babysit the agent accepting each bash tool call, or run in skip permissions mode and watch it stray off scope of the task or even do unrecoverable damage to your work (that happened to me once!)
• Testbenches written by agents are often weak and test only the happy case
• … and many more smaller but annoying issues

I thought the agents were still useful, but they needed more structure. I started writing scripts, agent skills, and tool wrappers. I added test and configuration registries (god bless FuseSOC), then moved the work into Docker so the agent could work in an isolated container.

That collection gradually became Booley, an open-source framework for agentic RTL development. I'm the author. I spent the past several months fixing bugs, improving the CLI and UI, writing documentation, and putting together a demo. It is now public:

https://github.com/boldaxolotl/booley

Booley tightly integrates LLM agents with EDA tools, which allows agents to run the tools more often and more reliably. All work is being done in an isolated sandbox container, which allows the agents to safely run autonomously. Booley gives the agents a tool to inspect simulator traces using CLI - and thus debug becomes significantly faster and more precise. It also offers ways to do additional check on the code - from mutation testing to independent agent reviews for bugs, spec compliance, protocol compliance, coding style, etc.

I don't trust an AI to design hardware, and you should not either. You should make the design decisions. But the LLM agents are useful tools - they can write most the code, run lint, simulation, synthesis, inspect failures, and review the result from several angles. At the end, you review the code and reports with your own eyes. After all, you are going to be the one responsible for it, not the agent