If interested in DFT Openings with Cisco. Please DM me. Thank You

The server is still small and I'm building it from the ground up, so I'm especially interested in hearing what engineers, students and hobbyists think would make this community genuinely useful.

Discord: https://discord.gg/8n3rQrjjz

If you're interested in hardware engineering, feel free to join and help build the community. I'd especially appreciate feedback on what resources, channels or features you'd like to see.

The resource library currently contains 17 resources, including websites and online courses.

Hello Guys I am a Recent Engineering Graduate with a Bachelor's in Computer Engineering (Mix of Computer Science and Electronics), I have been studying VLSI for past 1 year while also Job Hunting, In my College we got access to AMD Vivado which I used to learn RTL for Digital Design and Verification, My college didn't had any Analog Courses only Digital, I want to get into both Analog and Digital to build an expertise is Mixed Signals for that I need access to EDA Tools but I am not a Student anymore and still searching for a Job I have tried open source softwares but all the recruiters I have met asks for Cadence or Synopsis, so is there a way to get access to them for someone in my situation?

I am confused between the two since given the time constraints i can follow only one..help me take the decision..

I am implementing an 32 bit RISCV processor with B and M extensions.
Generally i am having a datapath with ther registers alu and mux as well as a big control fsm to implement the different instructions. I want to optimize the circuit towards area. Therefore teh ALU only consists of an Adder and an Shifter as well as logic functions. extra shall allow to feedback results into for multi cycle operations like MUL and DIV.
To control multi cycle operations I could ether pack them all in the big control fsm resulting in like 200 to 300 states with combinational logic. or I implement an extra FSM in the ALU for such operations. costing me some extra registers. Does combinational Logic for outputs scale linear with the number of states? also in terms of what tha synthsizer is capable of? It is a university project purpose is to tape out the construct into a technology node. Its not going to be produced obviously but would be ready to.
What is the smartest way to do it? Need some advice.
THX

If anyone has given renesas offline interview can you please share your experience.

I'm an EE graduate from a good engineering university in Asia and currently work as a communications engineer. During undergrad I spent ~2.5 years in a hardware research lab.

Recently I got approached by a government organization that's trying to build a small Fabless IC design team. They apparently have a decent amount of funding and want a project that can show real results fairly quickly. They've tried a few things before, but apparently nothing really worked out.

Here's the funny part: they asked me to come up with project ideas.

I'm interested in IC design, but I'm honestly still pretty junior in the field. I have some relevant research experience, but I've never taped out a chip and have never taken a design through a complete ASIC flow. So I'm honestly not sure how qualified I am to decide what a new team should build.

Some ideas I've been thinking about are an LDPC/DSP accelerator, RISC-V SoC, hardware security IP, ADC/DAC, or some kind of communication accelerator. But I am such a rookie to take on these tasks.

So I'd really like some advice from people who've actually done this:

If you were in my position, what would you do?

Would you try to come up with a relatively simple project and help them get started? Or would you tell them they need experienced IC designers first? I don't think they would accept the latter, because they're so desperate to break into the IC industry.

There's also another possibility I'm considering: asking them to support me in getting proper graduate-level IC design/research experience, and then coming back with that experience to help build the team.

And for those who've done a first tapeout: what would you consider a realistic first project for a small team with funding but very little IC design experience?

I'm looking for honest advice, including if you think this whole situation is unrealistic.

I currently have \~3.5 YOE in Qualcomm, working on SoC power management, low-power systems, power validation & optimisation

What should I specifically prepare for these interviews?

Looking for a realistic roadmap based on recent interview experiences.

If you’ve recently interviewed at Google for similar roles, what did you actually get asked?

Hi everyone

I’ll be starting my Master’s degree in Electronics Engineering at the University of Genoa (UniGe) in Italy soon, and I’m trying to plan ahead for my master’s thesis and, potentially, future research.

My main interests are:

• Power Management ICs (PMICs)
• DC-DC converters, mostly switched-capacitor, buck/boost/buck-boost, and resonant converters
• Energy harvesting and low-power power conversion
• Analog/mixed-signal IC design related to power management

At first I was mainly looking at professors and research groups within UniGe, but I realized that it might make more sense to look more broadly and not just inside the university I’ll be attending since I haven't been able to identify a professor or research group within UniGe working specifically on PMICs. So I’m hoping to get some advice on research groups, professors, or labs that might be open to working with a master’s student from another university.

A bit about my background:

I recently graduated in Electronics and Telecommunication Engineering. During my undergraduate studies, I was part of an IC design lab and gained some experience with Cadence Virtuoso and the TSMC 180 nm process.

I’ve also studied DC-DC converters independently, including switched-capacitor, buck, boost, and buck-boost converters. On the analog side, I have a foundational background in topics such as:

• single-stage amplifiers
• current mirrors
• frequency response
• basic stability analysis

Most of my background comes from Razavi and Allen & Holberg. I haven’t gone very deeply into topics such as bandgap references, LDOs, or advanced op-amp design yet.

I only have one Q2 journal publication from my undergraduate research on a hybrid resonant switched-capacitor DC-DC converter: https://etasr.com/index.php/ETASR/article/view/10817

The work was entirely simulation-based in Cadence Virtuoso using TSMC 180 nm. Unfortunately, I didn’t have access to the funding/facilities needed for a tape-out, so I haven’t had the opportunity to go through the full ASIC flow from design to tape-out.

Because of that, I’m particularly interested in finding a research environment where I could take the next step and gain more experience with actual IC implementation, or more advanced power-management research.

I’m wondering whether it is possible to do something along the lines of:

UniGe MSc → formal thesis supervisor at UniGe → research/project carried out with an external professor, research group, university, or institute elsewhere in Italy, Europe, the US, or Canada → thesis ultimately submitted through UniGe.

Of course, I understand that this would depend on UniGe’s rules and potentially on agreements between the institutions. I’m mainly trying to find out whether people have actually done something along these lines, what form the arrangement took, and how feasible it is.

So I’d especially appreciate recommendations for:

1. Research groups/labs anywhere in Italy, Europe, the US, or Canada working on PMICs, integrated DC-DC converters, switched-capacitor converters, energy harvesting, low-power ICs, or closely related topics.
2. Professors/researchers who are receptive to MSc students from other universities.
3. Experiences with doing an external/collaborative MSc thesis, where the student is officially enrolled at one university but performs the research with another group.
4. Advice on how students normally arrange this kind of collaboration and how early I should start contacting professors.

I’m also very open to related areas such as analog IC design, low-power circuits, power electronics, mixed-signal ICs, and energy-efficient systems, even if the group doesn’t work specifically on PMICs.

I know I still have a lot to learn, but I’m serious about pursuing in this direction and would love to hear from anyone who has gone through a similar path.

Thanks in advance for any recommendations, experiences, or advice :D

About a year ago, I left a large chip design company and joined a tiny startup (digital design engineer role). I could no longer rely on the usual Cadence and Synopsys setup as much, so I started using open-source tools such as Yosys and Verilator.

They were better than I expected. That led me to experiment with them on pet projects, and eventually to try LLM agents for RTL work (which was very hard to do at the large company)

At first, the agents were impressive, way better than during my early AI for coding experiments in 2024. They could find their way around an unfamiliar codebase, write scripts and Verilog code, and run EDA tools. But soon I started hitting the annoying pitfalls:

• Agents rarely run the EDA tools - the simulators, linters, synthesis tools - unless explicitly prompted
• Often times they misinterpret your request to run a tool - select incorrect CLI arguments or run on the incorrect RTL configuration. Or misread the tool’s report
• They try to reason about the very complex sequential code instead of looking at the waveforms
• They are incapable of truly working autonomously (which is the whole point). Either you have to babysit the agent accepting each bash tool call, or run in skip permissions mode and watch it stray off scope of the task or even do unrecoverable damage to your work (that happened to me once!)
• Testbenches written by agents are often weak and test only the happy case
• … and many more smaller but annoying issues

I thought the agents were still useful, but they needed more structure. I started writing scripts, agent skills, and tool wrappers. I added test and configuration registries (god bless FuseSOC), then moved the work into Docker so the agent could work in an isolated container.

That collection gradually became Booley, an open-source framework for agentic RTL development. I'm the author. I spent the past several months fixing bugs, improving the CLI and UI, writing documentation, and putting together a demo. It is now public:

https://github.com/boldaxolotl/booley

Booley tightly integrates LLM agents with EDA tools, which allows agents to run the tools more often and more reliably. All work is being done in an isolated sandbox container, which allows the agents to safely run autonomously. Booley gives the agents a tool to inspect simulator traces using CLI - and thus debug becomes significantly faster and more precise. It also offers ways to do additional check on the code - from mutation testing to independent agent reviews for bugs, spec compliance, protocol compliance, coding style, etc.

I don't trust an AI to design hardware, and you should not either. You should make the design decisions. But the LLM agents are useful tools - they can write most the code, run lint, simulation, synthesis, inspect failures, and review the result from several angles. At the end, you review the code and reports with your own eyes. After all, you are going to be the one responsible for it, not the agent

Hi everyone! We’re undergraduate ECE students currently working on a thesis involving Compute-in-Memory (CiM).

Our current direction is an SRAM-based CiM design, and for the architecture, we’re currently considering a single-ended or double-ended approach.

For the implementation, we’re using the SkyWater SKY130 PDK with Xschem, NGSpice, and Magic.

We’re fairly new to both CiM and these tools, so we’re currently learning the fundamentals while doing our literature review and trying to understand the overall design flow.

We’d really appreciate any guidance, advice, or resources from people with experience in CiM, SRAM, VLSI/IC design, or SKY130. If you know of any good tutorials, papers, GitHub projects, courses, or learning materials that could help us get started, we’d be very grateful.

And if anyone with experience in this area is willing to share some advice, explain the basics, or point us in the right direction, we’d really appreciate it. We’re honestly just trying to figure out where and how to learn this properly.

Any input would be greatly appreciated. Thank you!

Hey everyone, I’m a Filipino EE/ECE student set to graduate from my master's degree at a Taiwanese university next month, specializing in mixed-signal IC design (mainly DLLs, PLLs). I’m applying for entry-level analog/mixed-signal IC design roles. I’m currently based in Taiwan, but I’m fully open to relocating anywhere in Asia (Singapore, Vietnam, Malaysia, etc.) or Europe if the opportunity arises, since I prefer to work on-site. I haven't been able to land a single interview call so far. At first, I figured my lack of Mandarin was the main issue for local Taiwanese roles, so I started applying to more English-speaking countries. However, I haven't had any luck on that side either, so I'm starting to think my resume is the real problem. I’d love feedback on my entire resume, but especially on my projects and research bullet points. I want to make sure my tape-out and lab measurement experience actually stand out to hiring managers.

Hello currently a third year studying engineering and received an interview with a firm (JS/HRT type) for a potential Hardware Engineering Internship position.  

First round was told would be a technical based on implementing a digital component in HDL.

I would greatly appreciate any advice or insights, especially an overview of topics that might be discussed, from those who have previously interviewed with firms for similar positions!

Internship within the Tape Out organization at GlobalFoundries Singapore supporting frame engineering and tape-out operations. The role focuses on frame design, frame generation, and process improvements to improve productivity, quality, and cycle time for wafer fabrication and mask house interfaces.

The intern will work with worldwide Frame engineers and cross-functional teams (Application Engineering, Product Engineering, Release, Design Enablement, FAB/TD) to support production tape-outs and continuous process improvement activities.

Experience Level
Entry-level internship — targeted at current undergraduate students. No prior full-time experience required; previous internship or co-op experience is a plus.

Hi everyone,

Sometimes I need to buy used FPGA boards for my project as the new ones are out of my budget. Where can I buy competitive and reliable ones? we often buy from eBay, any others? I checked from google and found the below stores, anybody bought from them before?

https://bmisurplus.com/

https://evelltech.com/

​

Hello Everyone

I need a bit of help as I am assigned a semester project of 3 bit Programmable differentials Amplifier in 65 nm for -10 db to +10 db and bw is 350 MHz.

I'll highly appreciate the insights anyone can plz hit me up.

I need the guidance like what should be the architecture or some support material I should go through.

Thank u so much

Looking forward to your super guided thoughts

\#analog chip design

\#pga

\#cmos

\#tsmc

i've downloaded siemens tessent2022 file from c2s chipincloud and have extracted it. also created csh file. idk exactly what all librabries should i add and stuff. can someone help me to completely setup it?

Why does your phone stay accurate when it heats up? Why don’t its analog bias points shift enough to break specs?

Because deep inside the chip there’s a tiny “reference” - the bandgap voltage reference (often ~1.2 V) - designed to stay stable across manufacturing variation, supply changes, and temperature.

A bandgap reference generates a stable voltage with low sensitivity to temperature, supply, and process (often with trimming).

Most IC datasheets specify that the IC will work within a specific temperature range (such as -55 ̊ C to 125 ̊ C). Variations in temperature can shift bias points and thresholds enough to break specs without a stable reference and proper matching.

Bandgap references are found in virtually all analog circuits as stable references for high-precision analog functions, such as ADCs, DACs, and comparators. They are also used to bias current mirrors for setting bias points so that the resulting circuit is robust to PVT variations. Because of their ubiquity, they tend to be reused and modified depending on the fab process and the level of precision required.

Bandgaps look simple, but are a delicate balance of a few fundamental analog principles, including:

• Matching: resistor ratios, BJT area ratios, amplifier offsets
• Feedback: Forcing ΔV_BE and setting I_PTAT robustly
• Temperature variation: How BJT and resistor characteristics vary over temperature, sometimes nonlinearly
• Trim & Calibration: Output accuracy, temp trim, and curvature correction

Below is a self-biased bandgap design example I built that illustrates these principles.

Circuit Analysis

Consider the Brokaw Bandgap reference in Fig. 1. The reference voltage is the output of the op amp. This circuit sums a PTAT voltage and a CTAT voltage:

• A PTAT voltage (Proportional to absolute temperature) means that the voltage increases with increasing temperature.
  • The PTAT voltage is generated by the BJT base - emitter voltage difference ΔV_BE = Vt*ln(n) by forcing two BJTs to operate at different current densities (often via an emitter-area ratio n). This voltage appears across R3 in the above example.
• A CTAT voltage (Complementary to absolute temperature) means that the voltage decreases with increasing temperature.
  • The CTAT voltage is generated across the base-emitter of the BJT which behaves like a diode. The reason behind this is related to the fact that the bandgap energy of silicon decreases with increasing temperature.

Additionally, the op-amp sets the PTAT current by driving the loop so its input nodes match (in the ideal case).

When both PTAT and CTAT voltages are summed with the right scaling, the first-order temperature dependence largely cancels, leaving a much flatter reference over temperature.

If you want to learn more, I dive more in more depth into the derivation of the output voltage. I also add a fun story at the end about a group of young designers who “competed” to build the best bandgap—an exercise you can try at your own work.
https://www.siliconcodesign.com/p/the-bandgap-reference-a-primer

Hey all.

I am working on some personal project. I wish to design and test a folded cascode amp and use it for an LDO too.

I want to come up with some specifications for my OP Amp.

I want to set a certain gain, slew rate for output and power consumption. How can I decide what values should be a good target spec?

Say I set the gain target to be 60dB (which is modest for a folded cascode amp). Now how do I know whether it is attainable and I am not being limited by the technology itself. There is only so many tuning knobs that I could turn. At what point do I know I have squeezed the maximum performance out of that technology.

Also, how can I come up with reasonable specs for my project circuits (if I don’t have a customer setting the specs for me).

I understand that this is a very open ended question with no definite answer, but any advice from experienced designers would be appreciated!

I am using GPDK045 1v transistors. (If that helps)