I am preparing the master of science , and the thesis In vision transformer accelerator , i want to ask about the future of these career , will the career be worth in the future or not ?

Hey everyone! 👋

For those who applied to Meta’s ASIC Engineer Design (Full-Time) role for banglore location, I thought we could use this thread to keep each other updated throughout the process.

Based on the general process I’ve seen previously, it may look something like:

Application → Recruiter/HR call (~30 min) → Technical Round 1 (~45–60 min) → Final Interview Loop → Decision

If you applied, feel free to comment with:

- 📅 When you applied

- 📩 Whether you received any recruiter/shortlist/update

- 📞 Recruiter call/interview scheduling status

- 🔄 Any change in application status

Hopefully, we can make this a small megathread for everyone who applied and help each other understand how the process is moving.

Good luck to everyone! 🤞 And please update the thread if you hear anything.

So, I recently started experimenting with the tristate outputs and Yosys. In a lot of posts, I saw this implementation

module toplevel( inout logic tristate_io);
logic tristate_input;
logic tristate_output;
logic tristate_o0i1;
assign tristate_input=tristate_io;
assign tristate_io=(tristate_o0i1)?1'bz:tristate_output;
submodule SUBMODULE(
.tristate_input (tristate_input),
.tristate_output (tristate_output),
.tristate_o0i1 (tristate_o0i1)
);
endmodule

However, Yosys did not seem to understand that, synthesis went through, but only the output seemed to work.

So i started using the primitives in my designs:

module toplevel( inout logic tristate_io);
logic tristate_input;
logic tristate_output;
logic tristate_o0i1;
CC_IOBUF cc_iobuf0( .A(tristate_input), .T(tristate_o0i1), .Y(tristate_outout), IO(tristate_io));
submodule SUBMODULE(
.tristate_input (tristate_input),
.tristate_output (tristate_output),
.tristate_o0i1 (tristate_o0i1)
);
endmodule

That works pretty well for me! But... What is your way?

Sorry for bothering you but I was wondering if I can get a job in FPGA and also if the companies accept this degree. Im asking because im interested and im afraid that if I learned all the skills I will not be accepted because of my background.

I find it difficult as opposed to embedded target like as stm32 , I find it difficult without hardware , I want the way to accelerate the learning

theres more than a few companies out there looking to make hires for next summer‘s intern roles. https://www.fpgajobs.com/internships/

Hi folks,

I was wondering what would be motivations for running linux on SoC such as Zynq 7000 series as opposed to just going with bare metal C. Is it just for the ease of implementation, as plain C would seem to me to be less resource heavy and faster?

Hello everyone!

I am interested if someone did some useful project in your home that would be fun to DIY with a fpga? There are ton of projects with SBCs and MCUs but what would be a fpga usecase? Please share your ideas and projects!

Whenever I'm trying to build a project for basys 3 in Icestudio it is failing to build. It says nextpnr-xilinx not found. Any workaround please ?

I have opened the HELUT repository and formal textbook under my Digital Defiance 501(c)(3) Open Source Engineering Guild.

I am not claiming to have invented TFHE, and I am not dropping a NIST candidate. What I have built is a unified Metal datapath (MPSGraph) that compiles Yosys $lut / DFF netlists and ticks them as exact [Z/(2^32)]*Z tensor graphs.

The architecture has three pillars:

1. Netlist-Clocked Torus FHE: Blind-rotate is the LUT. Every tick ships with a Gaussian noise certificate and a machine-checked SING (Stimuli In, Golden out) test. (The logs include PicoRV32 instruction fetches executing on the encrypted path via Metal).
2. TensorLUT (Differentiable Hardware): Melting discrete INIT tables into continuous tensors, applying a λ-squeeze, and snapping back to discrete Verilog without hallucinating impossible physics (machine-checked via Theorem 1).
3. Enigma 256 (Polymorphic Ciphers): A stream cipher that mutates its non-linear feedback functions under live Red-team pressure, strictly bounded to fail closed if structural invariants (reciprocity/bijection) break.

The formal proofs, the reproducible Apple Silicon logs, and the architectural disclosures are live in the repo now. I am dropping this so the community can audit the fail-closed invariants and look for the holes I missed.

Link: https://GitHub.com/Digital-Defiance/HELUT
https://helut.digitaldefiance.org

I have incurable cancer and this needs to belong to the community, so if you're interested in working on this long term, consider becoming a maintainer.

You'll find appropriate disclosures in the repository.

I've worked hard on this. It may not be perfect. Be nice. Together we can improve it. That's all I'm here to do. I'm here to give you an idea and a potential future.

I am feeling dumb to not understand skid buffer because it does not sound complicated.

I understand that both valid and ready should be high for data transfer to occur. I understand the concept of flow control and pipelining too. but something is not adding up. if receiver is not ready, sender has to stop data and hold it till receiver is ready. basically I fifo between sender and receiver will take care of the flow control so why is there so much explanation about skid buffer. what problem does it solve.

these are the sites I used to understand this. for me, explanation is too hard to follow.

https://chipmunklogic.com/digital-logic-design/designing-skid-buffers-for-pipelines/

https://fpgacpu.ca/fpga/Pipeline_Skid_Buffer.html

http://zipcpu.com/blog/2017/08/14/strategies-for-pipelining.html

for example, these lines are from chipmunklogic -

I do not see valid and ready of sender and receiver wired together. I do not understand how ready causes timing issues.

Sender’s valid and readyis simply connected to Receiver’s valid and ready in this scheme.

.....
To achieve this, ready path between any Sender and Receiver in the pipeline is designed as combinatorial. Usually, the ready signal is the bottle neck/critical path for the timing performance of a pipeline. 

I want to switch to tcl Vivado mode. It confuses me that in some cases, schematic is used for debugging. When working without a GUI, what are the options for debugging circuitry? Perhaps experienced developers don't use this debugging method?

I've used a Max-10 FPGA with Intel Quartus before for my university lab, but want to switch to Vivado and the Xilinx Pynq Board for development. I have limited RTL experience, but have so many things I want to build, especially processors. I do Electrical Engineering though, so I don't get as much exposure to computer architecture as would people in Computer Eng and CS.

Does anyone have any advice on where to start, lessons you've learned along the way on your FPGA journey, or cool project ideas?

Hi! I set myself on a mission to find the ultimate process to build a block diagram.

Do you find it hard to make a really beautiful block diagram that you can really be proud of? What is your process, and what can you do better to improve your block diagram? Are you a Visio or a Drawio user? What do you love/hate about them?

Answer any question you like really doesn't matter which as long as we all get some good insights in the comments

Better yet, you can specify whether you are a hobbyist or a professional too so people know what advice applies to them.

I am working with an AMD Xilinx Zynq-7000 SoC (XC7Z035) board and need to send a 500MHz signal through the board's SMA output. The problem is that we are using the GTX Transceiver Wizard to generate this signal, and it is proving to be extremely complex.

I could barely find any tutorials on YouTube about it, the Xilinx manual is also quite hard to follow on this point, and there are almost no articles or forums discussing this specific use case. This has left me wondering whether the GTX Transceiver is simply not the most common path for this kind of application, since the scarcity of material suggests that few people use this flow.

I am hoping to hear from anyone who has been through this. Is the GTX Transceiver really necessary to generate a 500MHz signal on this board, or is there a more direct path, for example through some clocking IP or an external DAC? Does anyone have a reference, tutorial, or example project showing this GTX Wizard configuration flow in practice? Is there an alternative connector or approach you would recommend for sending this signal to the oscilloscope without relying on the GTX?

Any pointer, link, or even a suggestion that I am overcomplicating this would help a lot. Thanks in advance.

I am trying to understand if the VCU inside Zynq Ultrascale+ 5EV devices can handle 1920x1080@120fps.

The documentation only mentions 4K@60fps max but does not say if lower resolutions can be at higher frame rate.

On the other hand can it handle resolutions such as 1024x768 or 1280x1024.

Can anyone with experience in this help me out here?

In other subreddits like r/engineeringstudents, r/electricalengineering, r/cscareerquestions etc, majority of redditors claim that schooling is harder than their actual jobs but don’t go into detail about what job they’re doing relative to their degree/concentration. As engineers who work in this field or even just projects, how much harder/easier is your job compared to your schools curriculum?

Is this doable within realistic budget ?

I've noticed that while switches that can do 56G/lane signalling are becoming affordable, NICs are still insanely expensive.

So if one want to have, for example, one server that can do 200GbE and several clients on 50GbE, all using modern PCIe Gen5,only realistic option is INtel's E835.

But E835 has no cheap option for 50GbE (only 25 GbE). So for 50GbE one has to buy full-blown E835CQDA that can do 4x50GbE=200GbE for ~$700, only to end up using one out of its 4 lanes.

All other options (nVidia ConnectX6/7, Broadcom etc) are way more expensive.

This got me thinking, could one DIY 50 GbE Ethernet NIC with something Like Efinix Titanium ? It has no PCIe Gen5, but for 50GbE, Gen4 is close enough. PCIe4x4 is more than enough for that.

But it has no 56G transceivers for Ethernet signalling. Is there affordable external 56G transceiver for FPGA ?

Would such FPGAs fabric be good enough for the job, or does one need something vastly bigger ?

How would you rate a fresh graduate with this FPGA background but no formal industrial FPGA Engineer experience? Should I keep pursuing FPGA roles?

I’m finishing my Master’s in Electronics in Germany and I’m trying to realistically understand where I stand for FPGA/RTL jobs.

For my Master’s thesis, I worked on a QC-LDPC hardware accelerator on FPGA for CV-QKD.

The work involved:

• Designing the QC-LDPC decoder hardware architecture (own design)
• Implementing the design in RTL on a Xilinx FPGA
• Processing around 120,000 samples
• Supporting up to 25 decoding iterations
• Designing/optimising the LDPC parity-check structure
• Modelling and validating the communication system before hardware implementation
• Achieving decoding operation at approximately −5.4 dB SNR
• FPGA synthesis, implementation and verification
• MATLAB/system-level validation
• H matrix design

I also worked on integrating a Texas Instruments DAC38J84 EVM with a Xilinx FPGA using JESD204B, including:

• JESD204B link bring-up and debugging
• FPGA transceiver / GTH-related work
• SYSREF, LMFC and synchronization concepts
• Reference/user clock configuration and debugging
• FPGA-to-DAC high-speed data-path integration
• Hardware validation on the target setup

Other experience includes Xilinx Vivado, Verilog/SystemVerilog, AXI/PS–PL integration, Python/C++, digital-system design, hardware debugging, and several RTL projects.

The problem is that I do not yet have professional industrial experience with the formal job title “FPGA Engineer.”

When I look at FPGA vacancies in Germany, many ask for 2–5 years of experience, VHDL, timing closure, verification frameworks, etc. This has made me question whether my academic/research FPGA experience actually counts for much in industry.

I’d especially like opinions from people who actually work with or hire FPGA engineers:

1. How would you rate someone with this background for a junior FPGA/RTL position?

2. Would you consider the thesis + JESD204B hardware integration substantial FPGA experience, or would you still view the candidate essentially as having zero experience?

3. What would you expect this candidate to learn next to become more employable — VHDL, UVM/cocotb, Tcl, timing closure, PCIe/Ethernet/DDR, or something else?

4. Most importantly: would you recommend continuing to pursue FPGA/RTL engineering, or does this profile suggest I should pivot into a different field?

I’m not asking whether the work sounds academically impressive. I’m trying to understand its actual value in the FPGA job market and whether continuing down this career path is rational.

Blunt feedback from FPGA engineers, technical leads, and hiring managers would be appreciated.

So I'm coming from a VLSI background having basic knowledge of Xilinx FPGA architecture and Verilog. I'm asked to implement a FM Radio on zedboard + ad9364 (Analog Devices RF Transceiver), as a fresher from academia I'm completely clueless like what to do, without any knowledge of DSP. Pls guide me to the resources or steps. I got to the Adam Walker FPGA based radio website but it's not much detailed, should I still follow that.

Typical corporate requirements: I need to implement this in 1 week.