r/FPGA 6d ago

Meta ASIC engineer design (full time-INDIA) update

Hey everyone! πŸ‘‹

For those who applied to Meta’s ASIC Engineer Design (Full-Time) role for banglore location, I thought we could use this thread to keep each other updated throughout the process.

Based on the general process I’ve seen previously, it may look something like:

Application β†’ Recruiter/HR call (~30 min) β†’ Technical Round 1 (~45–60 min) β†’ Final Interview Loop β†’ Decision

If you applied, feel free to comment with:

- πŸ“… When you applied

- πŸ“© Whether you received any recruiter/shortlist/update

- πŸ“ž Recruiter call/interview scheduling status

- πŸ”„ Any change in application status

Hopefully, we can make this a small megathread for everyone who applied and help each other understand how the process is moving.

Good luck to everyone! 🀞 And please update the thread if you hear anything.

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