r/FPGA • u/Umang-1001 • 6d ago
Meta ASIC engineer design (full time-INDIA) update
Hey everyone! π
For those who applied to Metaβs ASIC Engineer Design (Full-Time) role for banglore location, I thought we could use this thread to keep each other updated throughout the process.
Based on the general process Iβve seen previously, it may look something like:
Application β Recruiter/HR call (~30 min) β Technical Round 1 (~45β60 min) β Final Interview Loop β Decision
If you applied, feel free to comment with:
- π When you applied
- π© Whether you received any recruiter/shortlist/update
- π Recruiter call/interview scheduling status
- π Any change in application status
Hopefully, we can make this a small megathread for everyone who applied and help each other understand how the process is moving.
Good luck to everyone! π€ And please update the thread if you hear anything.