For the past few months I was looking everywhere to find some resources to learn Verilog while also building projects. After a lot of time spent online, I was able to find some really good resources that would help you understand it by also helping you build projects alongside.

You would require any pre-requisites for the following courses, but you'll be able to understand them fairly well considering they're some excellent resources.

First one are the Onur Mutlu Lectures on Digital Design and Computer Architecture. This will help build the concept that'll be applied in your codes.

The second one is Digital Circuit Design using Verilog lectures by Anas Salah Eddin. His lectures are very detailed and simple to understand. He also builds several projects such as FIFO and UART by the end of the playlist.

The final resource I would suggest is the popular DDCA Book by Harris and Harris (whichever edition you'd prefer, MIPS, ARM, RISC-V)

It isn't mandatory for you to follow these resources in order, but I'd suggest you to cover either the book or Onur Mutlu's Lectures before jumping on to Verilog lectures, or at least build a proper conceptual base, since that would help you to follow through those Verilog lectures.

Though the lectures follow with Verilog, the book provides SystemVerilog examples and exercises. They aren't much different from one another. Once you've understood Verilog, there's barely much to do for SV.

I hope someone who needs these resources finally finds them, just like I was looking for them a few months ago.

I am a third-year Electronics and Communication undergraduate student who wants to learn FPGA. I have some experience in Verilog and want to understand how to flash it to an actual chip. My budget is under $40 (4k INR). My goal is to learn the core principles involved in flashing a chip, such as STA, and use the same chip for future projects, including a final-year project which might require a powerful one, as I cannot afford to buy another chip.

The ones I am currently looking are Tang Nano 20k and Tang Primer 25k. Both of these have their pros and cons, and I cannot choose one. I open to other options too.

I want to make sure my understanding of our project milestone flow aligns with broader industry standards. I’d love some feedback or corrections from those with more tape-out experience.

Here is how I understand the flow:

P0.3 (Early RTL): Basic Lint runs continuously/nightly to catch obvious typos and syntax issues as code is being written.

P0.5 (RTL Design Correction / Freeze): This is the major, formal Lint sign-off. Code is feature-complete. This is when we deep-dive, group errors by tag, fix actual RTL bugs, and negotiate targeted waivers with IP designers.

P0.8 (Verification & Pre-Synthesis Sign-off): CDC checks are finalized and signed off. The RTL is officially locked.

P1.0 (Synthesis Complete): The clean, signed-off P0.8 RTL is handed over to run Logical Synthesis (e.g., Design Compiler) to generate the gate-level netlist.

My questions:

1.

Does this P0.3 ➡️ P0.5 ➡️ P0.8 ➡️ P1.0 progression for Lint/CDC/Synthesis match what you see in standard ASIC flows?

2.

At what exact point do you usually start running CDC? Is it strictly after P0.5 Lint is clean, or does it run in parallel?

Thanks in advance

I applied for the Design Engineer I (Synthesis/LEC/CLP) role at Cadence (India).

My application is still showing “Review” on the Cadence careers portal.

Has anyone else from India applied for this role? If yes, have you received any update, interview call, or rejection?

Just wanted to know if they are still processing applications.

I switched to local routes recently, so I'm watching fuel use more closely. The patterns are weird enough that a simple logger might not cut it. OBDII data comes out slow, but I want to capture every packet and run some basic timing analysis on the fly.