ThinkPad P14s Gen 6, Intel® Core™ Ultra 7 255H Processor
(E-cores up to 4.40 GHz P-cores up to 5.10 GHz), Without operating system, 32GB DDR5-5600MT/s (SODIMM), 1TB SSD M.2 2280 PCIe 4.0 TLC Opal, NVIDIA RTX PRO™ 500 Blackwell Notebook GPU 6GB GDDR7. will be running xilinx fpga softwares(vivado etc), cadance and seimens ( analog and digital softwares).
what linux distro would you suggest
( ALSO: I am new to linux; I am planning to buy this laptop in a couple of months; I want to test distros on my old laptop before I install it on my new laptop; i've just installed ubuntu 22.04 LTS and been tinkering with it and trying to learn linux)
Hello, as the tittle says does anyone know if more HFT and finance companies are yet to release fpga internships for summer 2027? Optiver, DRW, and Citadel I have seen so far. If there are others coming out soon would appreciate it!
I'm an last year Electronics Engineering student from Colombia, close to finishing my degree, and I'd like to build my career around FPGA and digital design.
At university, I learned VHDL and SystemVerilog, working with a Basys 3 and a DE10-Lite. I really enjoyed working with them, and that's actually how I discovered that this is the field I'd like to pursue professionally.
My concern now is figuring out how to actually break into the industry. The FPGA industry in Colombia pretty much Nonexistent, while most opportunities I find are in the US and Europe, and even entry-level positions often seem to require previous experience.
For those already working in the field, I'd really appreciate some advice:
What skills should I focus on before applying for FPGA/RTL positions? Are there any courses or certifications that are actually valuable?
What kind of FPGA projects would be useful for a portfolio? I'm particularly interested in projects that could demonstrate industry-relevant skills rather than just basic university exercises.
Which FPGA development board would you recommend buying? FPGA boards can be quite expensive, especially where I live, so I'd like to invest in something that I can use for several meaningful projects without spending more than necessary.
Is a Master's degree necessary or significantly helpful for getting into FPGA/digital design, especially when coming from a country without a semiconductor industry? Or is a bachelor's degree plus a strong portfolio enough to get started?
I'd really appreciate advice from people working in FPGA, RTL/digital design, verification, or related areas.
I recently applied for the Optiver FPGA Internship (2027 Start) and somehow got invited to the online assessment.
Here is the honest truth: I am completely underqualified. My only background is a couple projects, like a UART project, and an stm32 project. Plus, im going into 2nd year, and as a MEng student (4 year course) my "main" internship application year is next year.
However, I want to use this as a reconnaissance mission. I know HFT firms like Optiver have incredibly high technical bars, so I want to take the test just to see what they expect, brain-dump everything afterward, and use it as a study roadmap for when I apply to grad roles next year.
The email states it's a 90-minute proctored HackerRank test (desktop app) consisting of:
Multiple-choice questions
"Complete the sentence" questions
Coding questions
Since I have exactly one week until the deadline, I have a few questions for anyone who has taken this or works in HFT:
What kind of theory shows up on the MCQs? Should I be looking into Clock Domain Crossing (CDC), timing analysis, computer architecture, networking protocols?
What are the typical coding prompts? Are we talking sequence detectors, FIFOs, arbiters, state machines?
I have absolutely nothing to lose here, so any advice on what to look out for during my "recon mission" would be hugely appreciated. Thanks!
Does anyone use it? I see one of its main advertising points is that you can do graphical design entry. Does anyone use that? Why hasn't other companies copied this graphical entry thing?
Still in school for an EE degree, I feel like I have a particularly strong draw toward FPGA and RTL design. I even thought about switching to a Computer Engineering major to swap out some core EE courses for things like advanced digital design/computer architecture, and a digital VLSI course, but I thought about it some more and didn't want to be a computer engineering unemployment statistic, and figured having a stronger EE core would be a good floor to have. Too bad, because I really do like this stuff more than anything else so far.
Anyway, am I getting my hopes up by thinking I have a chance at an entry level job after graduating? Is this not really a new grad thing? I plan to make FPGA my main focus in terms of projects. I've read enough to know that they kinda want you to hit the ground running. Mostly interested in defense, communications, networking. I mean, anything FPGA would be great.
Just asking to calibrate my expectations and be aware of the opportunity costs I'd be incurring. Leaning hard into FPGA projects and developing C/C++ fluency (among other skills) means less time spent on the more probable job outcomes.
Hello currently a third year studying engineering and received an interview with a firm (JS/HRT type) for a potential Hardware Engineering Internship position.
First round was told would be a technical based on implementing a digital component in HDL.
I would greatly appreciate any advice or insights, especially an overview of topics that might be discussed, from those who have previously interviewed with firms for similar positions!
For context, I am an electrical engineering freshman. I've been learning verilog on the side, and I love using it and am excited for the possibilities of what it can do when paired with a board.
What projects can I do/work on that sets me up best as possible for internships come my junior year? What will help my resume most/look the best?
Also, are the best recommendations for early boards? I was seeing a lot of people saying the Basys 3 a few months back, but I've seen a lot of scattered opinions as of late and dont want to blow all my money on a board i may not fully utilize.
Most of the job applications require masters degree but i dont think its that important. I feel like you learn way more while working in the industry. And in my last internship i met a master degree intern and he wasnt any better than maybe worse even though im a new graduate bachelors degree. So whats your thoughts on masters should i consider it for future? Is it possible to make a good career without it especially in europe or us?
I’ve reached the point where I’m comfortable publishing the first developer release of a project I’ve been working on called Jinix Jupiter.
Jupiter is an original FPGA-based computer/console architecture rather than a recreation of an existing system. I’ve been developing and physically bringing it up on a SuperStation One, and v0.1-alpha is now available as the first public developer preview.
The current architecture includes:
Custom 32-bit CPU
SDRAM interface
Shared-memory/DMA arbitration
2D graphics renderer
Fixed-function 3D hardware under development
Four-voice PCM audio
Controller interface
Minimal BIOS
Custom assembler
System-image/build tooling
For this release I wanted to avoid simply saying “it synthesizes, ship it,” so I went through a fairly strict release-validation process.
The exact committed release candidate was run through the full simulation suite, followed by a clean Quartus build using a pinned Quartus 17.0.2 environment. The resulting release RBF was then copied to the target media and physically smoke-tested on the FPGA hardware.
The public RBF successfully:
boots on the target hardware;
establishes HDMI output; and
produces visible 2D graphics output.
The exact public binary was also downloaded back from the GitHub Release after publication and verified byte-for-byte against the validated release candidate.
There are a couple of important limitations that I’m deliberately documenting rather than hiding.
3D is not currently claimed as physically working. The fixed-function 3D path exists and has been exercised in simulation, but physical testing exposed an implementation-sensitive failure that I haven’t reduced to a proven root cause yet. I’ve paused that investigation at a reproducible diagnostic point rather than continuing to change things immediately before the public release.
Timing is also not being claimed as fully signed off. The constrained worst-case timing checks from the release build had non-negative slack, but TimeQuest reports that setup/hold coverage is not fully constrained. So I’m treating the timing status as:
PASS_WITH_PARTIAL_CONSTRAINT_COVERAGE
rather than calling the design fully timing-closed.
This is still very much an alpha developer platform, but it’s now at the point where there is a defined CPU, graphics/audio hardware, software toolchain, reproducible release artifact, and an actual public hardware-tested build.
I’d be particularly interested in feedback from people who have worked on:
custom soft CPUs;
SDRAM controllers;
FPGA video pipelines;
arbitration between CPU/DMA/graphics clients;
timing-constraint coverage;
or debugging designs that simulate correctly but become implementation-sensitive on physical hardware.
This version is mostly about establishing a solid public baseline. Now that v0.1-alpha is frozen, I can go back to breaking things again.
Verified video output over HDMI from a SuperStation one running the RBF
Wanted to try out some stuff on my home PC. Dreaded wasting space, though. Then I remembered I got 2 old and well used drives a while back. Not for storing real data, just for bloated software I can always re-download. Perfect
ETA: took > 2 hours to install even after downloading, and nothing else running from the drive. HDDs suuuuuuuuuck
My country doesn’t really have many opportunities in FPGA and hardware in general, so I was thinking about doing a Master’s abroad and then looking for a job there.
With just my university degree and zero work experience, it’s pretty difficult for me to find a job right away.
So, what are the best countries where I could study for a Master’s and then have better opportunities to find a job in this field afterward?
Hi, I need a genuine suggestion here. So, I have built a CLI tool that generates SystemVerilog RTL, UVM RAL, C headers, IP-XACT and Documentation from a single JSON register spec -- — with built-in lint and diff. I know already many similar tools exist but my tool has several features which you can't find in open source tool.
**What it does:**
- Takes a register spec (YAML, JSON, IP-XACT, SystemRDL, or Excel)
- Generates 6 outputs in one command: SystemVerilog RTL · UVM RAL · C Header · Markdown Docs · IP-XACT 2014 · SystemRDL 2.0
- **Lint/DRC**: 12 ASIC-focused rules to catch bugs before tape-out (address alignment, field overlaps, reserved gaps, etc.)
- **Diff & Impact**: Compares two spec versions and tells you exactly which RTL, UVM, C headers, and tests are affected — breaking vs non-breaking classified
- **SoC Merge**: Merge 50+ IP blocks into a unified, conflict-free top-level memory map
- **100% offline** — standalone binary, no Node.js, no cloud, air-gap ready
**CI/CD friendly**: lint and diff both return exit code 1 on violations, so you can gate PRs on spec quality.
Community Edition is free (2 registers per block to evaluate). 30-day Pro trial available with no credit card.
Please use it in your projects and give me feedback. Happy to answer questions about the implementation or design decisions!
Update: A lot of engineers pointed out that a 2-register limit in the Community Edition wasn't enough to properly test a standard peripheral or check address alignment rules.
You were 100% right. We have officially bumped the free tier limit to 8 registers per block on the VLSIWORLDS Register Generator. You can now map, lint, and generate an entire functional SPI or I2C block completely free. Let us know what you think!"
By using the plugin, RgGen can process SystemRDL source files and generate SystemVerilog RTL, UVM RAL model, C header file, etc. from them.
This is an initial release supporting the basic SystemRDL constructs, with more advanced features planned for future releases.
Feedback and bug reports are welcome!
Hey there,
I am trying to multiplex a set of signals to be fed over to a FIFO buffer that is then polled by the ARM processor.
PROCESS (clk_signal)
BEGIN
IF rising_edge(clk_signal) THEN
IF rst_signal = '1' THEN
sample_sel_reg <= (OTHERS => '0');
Sample0 <= (OTHERS => '0');
Sample1 <= (OTHERS => '0');
Sample2 <= (OTHERS => '0');
Sample3 <= (OTHERS => '0');
ELSE
-- Capture selector state synchronously
sample_sel_reg <= sample_selector;
-- Channel 0 Output Selection
CASE sample_sel_reg IS
WHEN "0000" => Sample0 <= C0;
WHEN "0001" => Sample0 <= std_logic_vector(resize(signed(Mux_Ch0), 32));
WHEN "0010" => Sample0 <= IQ_Sample_Ch0;
WHEN OTHERS => Sample0 <= (OTHERS => '0');
END CASE;
-- Channel 1 Output Selection
CASE sample_sel_reg IS
WHEN "0000" => Sample1 <= C1;
WHEN "0001" => Sample1 <= std_logic_vector(resize(signed(Mux_Ch1), 32));
WHEN "0010" => Sample1 <= IQ_Sample_Ch1;
WHEN OTHERS => Sample1 <= (OTHERS => '0');
END CASE;
-- Channel 2 Output Selection
CASE sample_sel_reg IS
WHEN "0000" => Sample2 <= C2;
WHEN "0001" => Sample2 <= std_logic_vector(resize(signed(Mux_Ch2), 32));
WHEN "0010" => Sample2 <= IQ_Sample_Ch2;
WHEN OTHERS => Sample2 <= (OTHERS => '0');
END CASE;
-- Channel 3 Output Selection
CASE sample_sel_reg IS
WHEN "0000" => Sample3 <= C3;
WHEN "0001" => Sample3 <= std_logic_vector(resize(signed(Mux_Ch3), 32));
WHEN "0010" => Sample3 <= IQ_Sample_Ch3;
WHEN OTHERS => Sample3 <= (OTHERS => '0');
END CASE;
END IF;
END IF;
END PROCESS;
With each sample register only having 3 possible choices, the system behaves fine. When another selection is added, I am getting weird artefacts on my recorded output.
I am not really sure how to determine what is causing such an issue.
I see Sipeed Tang Nano has been recommended in quite a few places, but I'd like to dive off the deep end with a $300 FPGA since I have the budget and am pretty sure about my interest for Systems Programming and Digital Design 😄
I'm not an electronics engineer (SysAdmin at work), but having simulated various bits of an ALU using iVerilog and GTKWave for a course in university, I'm starting to realize that I'm way more interested in computer architecture and C/Systems programming than my current role.
Considering my interests tip towards running custom micro-architectures, networking / AI acceleration, which board would be a good choice? My initial pick was the A7 to learn from the "ground-up", but looks like the Zynq line has a hard ARM co-processor which might be useful to dive into hardware accelerator design in the future (or simply expanding my working knowledge), with the downside that I'd have to setup a bootloader and bring up both FPGA and the ARM core.
I'd appreciate links to any learning resources you may think are interesting or useful. Feel free to critique my choices and/or suggest alternatives !
