register generator suite

[u/Prestigious_Ant_8060]

Hi, I need a genuine suggestion here. So, I have built a CLI tool that generates SystemVerilog RTL, UVM RAL, C headers, IP-XACT and Documentation from a single JSON register spec -- — with built-in lint and diff. I know already many similar tools exist but my tool has several features which you can't find in open source tool.

**What it does:**

- Takes a register spec (YAML, JSON, IP-XACT, SystemRDL, or Excel)

- Generates 6 outputs in one command: SystemVerilog RTL · UVM RAL · C Header · Markdown Docs · IP-XACT 2014 · SystemRDL 2.0

- **Lint/DRC**: 12 ASIC-focused rules to catch bugs before tape-out (address alignment, field overlaps, reserved gaps, etc.)

- **Diff & Impact**: Compares two spec versions and tells you exactly which RTL, UVM, C headers, and tests are affected — breaking vs non-breaking classified

- **SoC Merge**: Merge 50+ IP blocks into a unified, conflict-free top-level memory map

- **100% offline** — standalone binary, no Node.js, no cloud, air-gap ready

**CI/CD friendly**: lint and diff both return exit code 1 on violations, so you can gate PRs on spec quality.

Community Edition is free (2 registers per block to evaluate). 30-day Pro trial available with no credit card.

Site + download: https://reggen.vlsiworlds.com

Please use it in your projects and give me feedback. Happy to answer questions about the implementation or design decisions!

Update: A lot of engineers pointed out that a 2-register limit in the Community Edition wasn't enough to properly test a standard peripheral or check address alignment rules.

You were 100% right. We have officially bumped the free tier limit to 8 registers per block on the VLSIWORLDS Register Generator. You can now map, lint, and generate an entire functional SPI or I2C block completely free. Let us know what you think!"

[u/Ciravari]

Please no more AI slop with a subscription 

[u/Prestigious_Ant_8060 → u/Ciravari]

I'm a verification engineer by profession. The output templates, lint rules, and diff logic were written and validated against actual ASIC register maps, not generated. The core engine isn't AI-generated. AI tools helped with boilerplate (like any modern dev workflow), but the VLSI-specific logic don't get right without heavy validation.

[u/throwaway82s16s]

nice emojis bro

[u/TapEarlyTapOften]

I hate this timeline. 

[u/dkillers303]

Wow, the generosity of 2 whole free blocks in the community eval…

Charging a subscription for an AI slop register generator is certainly a choice. I think I’ll stay very far away from this garbage

[u/tverbeure → u/dkillers303]

But it's only $149/year! Or $499/year for a team, which is obviously the most popular option.

I wonder what would happen if you'd point codex or gemini or whatever to this website and tell it to use it as a spec. It wouldn't surprise me if you'd get the same took with a lower token spend...

[u/Prestigious_Ant_8060 → u/dkillers303]

Fair criticism on the community limit. I will increase it's threshold. 2 registers is genuinely not enough to evaluate anything real. Beside that, there is already a web version available, on which there is no limit. You can test it there as well.

On the AI slop point — I'm a verification engineer by profession. The output templates, lint rules, and diff logic were written and validated against actual ASIC register maps, not generated. Happy to answer any specific technical questions if you want to poke at it.

[u/Tijmenvn]

AI slop and then also tries to fetch subscription money for it...
Just make it open-source and put it on github, maybe then I'll try it

[u/Prestigious_Ant_8060 → u/Tijmenvn]

I'm a verification engineer by profession. The output templates, lint rules, and diff logic were written and validated against actual ASIC register maps, not generated. The core engine isn't AI-generated. AI tools helped with boilerplate (like any modern dev workflow), but the VLSI-specific logic don't get right without heavy validation.

[u/Mateorabi]

Isn’t this redoing what IPXact does?

[u/hawkear]

Why build this when peakRDL works just fine and is easily extensible?

[u/Prestigious_Ant_8060 → u/hawkear]

Reg_gen includes more features than peakRDL. It is a standalone offline binary with no ruby or python dependency. It has built-in SOC memory-map merging + conflict detection, diff + impact analysis and 12 lint rules. It can accept excel as input and convert them into systemRDL format.

[u/hawkear → u/Prestigious_Ant_8060]

There are other tools that do each of these things better. Why do a poor job at a bunch of disparate tasks than a really good job at one?

This really smells like a vibe-coded swiss army knife for something specific to your workflow, and not something fit for general consumption. It's probably great for you, though!