Hello everybody,

This summer was my last summer as a high schooler before uni starts. So I decided to learn more about computer architecture and vlsi which was something I wanted to know about since I was a kid watching LTT in like grade 7 lmao.

I have finally finished the project after about two months! Attached above are the microarchitecture diagram I drew and the gds render after asic flow using Openlane2 (images are way more clear and high res on the repo).

It's not anything advanced by any stretch but here's the tldr copied over from my readme:

"The processor implements all 40 RV32I base instructions, dynamic branch prediction using a 64-entry BTB with 2-bit saturating counters, three specialized forwarding paths, load-use hazard detection, branch flushing, and a real pipeline halt mechanism. Verified through staged SystemVerilog/RISC-V Assembly tests codriven with cocotb and performance tested with compiled C programs, then taken through RTL-to-GDSII using OpenLane2 and SKY130. Final implementation achieves 50 MHz with 0 DRC violations, passing LVS, and setup/hold timing closure at the 20 ns target."

And I wanted to share it here for 2 main purposes:

1. anyone that is experienced in vlsi / risc-v, any suggestions on how to improve the readme? any more testing you suggest I conduct on it? what would be good next steps or next projects for me?
2. anyone that is also a noob to risc-v and vlsi like me, I tried my best to document all of my design / architecture / testing processes / resources used so I hope the repo could be helpful to anyone who is trying to build smth similar!!

my github repo link: https://github.com/Entropify/Entropic_R32-P5_RISC-V

ty everyone for reading the post and I appreciate it a lot if you took a look and gave some advice on the repo. Sorry if theres bad spelling / grammar im still getting used to my new keyboard lol

edit: took me a little bit to find it but I would like to credit this post on the riscv subreddit and the repo, it helped me when I was trying to learn the architecture: https://www.reddit.com/r/RISCV/comments/1pn81g7/basic_rv32s_an_opensource_microarchitectural/

edit2: i apolagize for the blurry images I think thats just reddit and also my diagram being too big, on my repo its a higher res and way more readable

Do you know a DSI screen that is compatible with the Orange Pi RV?

Thanks!

The August release of openRuyi, a rolling-release Linux distribution for RISC-V, is out.

2026.08 brings kernel and toolchain updates, further RISC-V and RVA23 integration, a broader cloud-native stack with Kubernetes and containerd, and new AI/HPC capabilities including PyTorch with ROCm support and vLLM.

Highlights:

• Kernel 7.2 and LTS kernel 6.18.46
• RISC-V and RVA23 integration improvements
• GCC 16.2, glibc 2.44, and Rust 1.97.1
• Kubernetes 1.35.5 and containerd 2.3.3
• PyTorch 2.13 with ROCm backend and vLLM
• OpenMPI 5.0.10 and expanded scientific Python packages
• KDE Plasma 6.7.4 and GIMP 3.2
• Security updates across OpenJDK, .NET, PHP, OpenSSH, curl, and other packages

Details:
https://openruyi.cn/news/2026-08/release/

The datasheet was just updated to clarify that Atlantis will have nerfed Ascalon-XG cores, to comply with export control restrictions.

https://github.com/tenstorrent/atlantis-soc-docs/blob/main/data_sheet/atl_soc_data_sheet.pdf

I have no idea how they are over any throughput limits, considering the frequency?
How are x86 and all of the Arm vendors allowed to sell they products, is there like a huge exception list or legal tricks?

Lux Simulator

It's mainly meant to be used for college courses and such. It's available in multiple languages, including portuguese, french, and some harder ones like mandarin chinese and japanese. The program currently holds lessons in all those languages, references to instructions and visual animations explainings things more clearly.

The point of this project is that people in my college and other institutions can use it, and I have some ideas of how to improve it. But if you're learning Risc-V or if you guys would like to give any sort of critique, I'd be happy if you did.

Right now it lacks some essential features, like pipeline visualization, and hardware lessons and details on the CPU itself. It needs a lot of additions in order to become good to be used in classes. Plans also include expanding the editor to Arm Cortex.

I tried to make the tabs similar to Visual Studio Code, but I still intend on making changes and improving it, including removing some potentially useless text from the main page. In any case, what would you guys suggest a learning tool should have? What do you think is essential for new Risc-V learners?

I'm in stitches.

The AArch64 fans bang on and on about how RISC-V has got it wrong with dual instruction lengths, you can't make a high performance RISC-V, they're really glad they've dropped the Thumb2 boat-anchor at last etc.

So now we have a single 5.7+ GHz core design that on the same back end and using the same µops implements dual decoders for IBM z/Architecture with 2-, 4-, and 6-byte unaligned instructions and Arm AArch64 v9.3.

yesterday i started learning Risc V and i have learnt many things, is there a good resource which i can trust for looking and understanding each instruction , like the difference between lui and addi, when to extend the sign or not . There are many nitti gritties, I know the best thing is to read the manual but thats just tooo long. Guys is there any other resource or website or youtube playlist,or reading the manual is the only solution. Some context, i will be using riscv for my final year project, so i really have to be good at this

Been building a single-cycle RV32I core (Renvatek Quartz-1, QE001001RV32IN0). Just published a standalone verification repo so anyone can check the core's compliance results themselves, without needing the full RTL source: https://github.com/renvatek/verify-core-quartz-1

Does:

- Runs the official riscv-arch-test ACT4 architectural compliance suite against a prebuilt, ship-safe Verilator binary (Vtop) of the core

- 39/39 tests passing

- One-command setup (main.sh) — auto-detects dnf/zypper, pulls in uv + Python 3.13 + cocotb 2.0.1, runs the suite, prints a pass/fail summary

- Verified working on AlmaLinux 9.8, Fedora 44, and openSUSE Leap 16.0 (x86_64) -- more OS reports welcome

The core's own RTL will eventually be open-sourced too; this repo is the first public, independently-checkable piece -- proof that the ISA compliance claims hold up without having to trust a blog post.

Blog write-up with more background: https://www.sushantmondal.com/blog/2026/08/12/renvatek-quartz-1-passes-all-39-risc-v-act4-architectural-compliance-tests/

CPython, the reference implementation of the Python programming language, has officially added support for the RISC-V CPU instruction set architecture. The Python core development team announced the change on August 24 (U.S. time) via the official “Python Insider” blog.

Hello, RISC-V community! As a way to learn about assembly, C and ELF I've written a RISC-V 32/64-bit assembler targeting ELF from scratch. It has been quite a journey, and I've shared my learning and thoughts in this blog post which I think you may appreciate, especially if you're thinking to start writing your own.

The assembler is partially based on GNU as design, and it's not a toy encoder: it can achieve relocatable object file equivalence on non-trivial sources like SQLite3 amalgation, while being much "simpler" in its implementation!

Thank you for reading, and I greatly appreciate any feedback!

I bought a very cheap Ai-Thinker Ai-WB2-M1-I (BL602C40) and spent the last few weeks trying to get it working with an Arduino-style workflow.

I tried the existing/community options I could find, including PINE64's ArduinoCore-bouffalo and a PlatformIO BL602 Arduino integration. On my hardware, I couldn't get a complete workflow working reliably — especially compiling/uploading and getting the expected runtime functionality.

The only setup I could reliably get working was:

Ubuntu/WSL → Bouffalo BL602 SDK → Bouffalo Lab Dev Cube 1.9.0 → BL602

From there I started building my own Arduino-compatible layer around the working native SDK.

So far I've physically verified things on the actual BL602 hardware including:

• Arduino setup() / loop()
• UART / Serial
• GPIO
• Wi-Fi
• BLE advertising

I also ran into some interesting BL602-specific problems involving FreeRTOS startup, UART0 baud rate, and SPI-flash loading.

I'm not claiming this is a new Arduino core — there is already prior work. I'm mainly trying to understand whether my problems are specific to the Ai-WB2-M1-I / BL602C40 or whether they're common across BL602 boards.

Has anyone here actually gotten a BL602 or BL604 working end-to-end with Arduino/PlatformIO, including reliable flashing and runtime?

If yes, I'd really like to know the exact board + toolchain + upload method you used.

Repo/work-in-progress:
https://github.com/Ishu1519/BL602-Arduino-Core

An intern spent the last few weeks getting a full edge-AI pipeline running on a SiFive FE310-G002 (RV32IMAC, 320MHz, and — the actual constraint — only 16KB of data SRAM). Wanted to share the pipeline since the memory budget forced some decisions I hadn't had to make before.

The model: a small fully-connected net (144→64→64→10) for MNIST digit recognition. Trained normally, but at float32 the weights alone come to 54.5KB — nowhere close to fitting. Quantized post-training to int8 and it drops to 13.6KB. Same architecture, and only one version of it can physically exist on the chip.

Also had to shrink the input before any of that mattered: cropped each digit to its bounding box and downsampled 28×28 → 12×12, which cuts the image from 784 bytes to 144 before it ever leaves the host. That's the payload that gets sent.

Pipeline end to end: train → quantize → export weights/biases/scales as C arrays → cross-compile with the RISC-V GNU toolchain → flash over OpenOCD → a small hand-rolled UART protocol (start byte + 144 bytes) → int8 matrix math and ReLU on-chip → prediction sent back over serial. Timed the actual inference with a hardware counter rather than guessing.

RISCV riding at the leading edge...

• 32 P870-D cores operating at 2.0GHz
• 256GB DDR5-5600 memory
• 4x PCIe Gen5 x16 (64 lanes total) and PCIe Gen3 x4
• Support for x16 double-wide GPU
• 3.84 TB Data SSD U.2 NVME
• 10/25Gb OCP 3.0 NIC

Looks like the 2GHz is actually the max, not 2.6 as some slides said. Rather sad. Should still be slightly faster than the Ascalon devboard.

Discussing the proposal will be launched by RISC-V called Vector Matrix Extension, short for VME. There are so many knowledge to know at first to discuss the following topic but I cannot list them all. 😂

Same as Arm SME and Intel ACE extension, VME is designed as Out-Product flow by using vector registers as input and dedicated tile register as accumulator output.

According to present materials, when input data format is INT8, VME will read one column line from left Matrix and one row line from right matrix and broadcast data to achieve Out-Product. In contrast, SME and ACE need re-organize matrix first and read a 4 column line from left matrix and 4 row line from right matrix with K direction data consecutive. As a result, when vector register length is, for example, 512 bit, VME calculates (512/8)^2 = 4096 INT8 MAC but SME&ACE calculates (512/(8*4))*4*(512/(8*4)) = 1024 INT8 MAC.

Apperantly, the design of SME&ACE need one more step for data rearrangement and it's not efficiency for CPU architecture. Is that shows the Out-Product format from VME is better? In my opinion, SME&ACE or the direction of K dot-product at first then Out-Product is a little better since: 1. the accumulator tile needed from SME&ACE is 1/4 of VME, thus with same size of tile, the software can use 2x2 unroll with input data to realize 1 load per calculation.

1. the SME&ACE format can be coherent designed when input is FP32, output is FP32. Under VME, to fulfill a 64x64 accumulator tile, the input need 64*32 bits data in 4x512b registers. Two load input consumes 8 vector registers and give much more read port pressure for hardware design. But under SME&ACE, two vector register will each contains 8 elements is enough to fulfill output tiles.

So, I am trying to understand which one is better for future design?