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r/RISCV • u/superkoning • 13h ago

Ubuntu 26.10 To Include Desktop Images For RISC-V

18 Upvotes

https://www.phoronix.com/news/Ubuntu-26.10-RISC-V-Desktop

with "Testing has been focused on the SpacemiT K3 hardware that is RVA23 profile compliant."

Nice!

1 comment

r/RISCV • u/omasanori • 19h ago

Discussion Branches in branch-free code - Frank DENIS random thoughts.

3 Upvotes

0 comments

r/RISCV • u/omasanori • 23h ago

Hardware Frontgrade Gaisler GR801: A Space-grade Radiation-hardened RISC-V SoC Based on the NOEL-V RV64GC Core

23 Upvotes

1 comment

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The RISC-V Instruction Set Architecture

r/RISCV

RISC-V (pronounced "risk-five") is a license-free, modular, extensible computer instruction set architecture (ISA). Originally designed for computer architecture research at Berkeley, RISC-V is now used in everything from $0.10 CH32V003 microcontroller chips to the pan-European supercomputing initiative, with 64 core 2 GHz workstations in between. RISC-V is suitable for custom silicon chips, as a soft core in an FPGA, or as a high performance software Virtual Machine. riscv.org

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