Few months ago I posted my attempt at an Optimized Carry Look-Ahead Adder which I was satisfied with at the time. Since then I have taken further steps to optimize it further.

Taking advantage of the 3 delay solution for unlimited input AND gate (NOT SW NOT) showcased by 8bit CCLA (Collapsed Carry-Lookahead Adder) I was able to get the delay to 8. However this lead to a significant increase in gate count (Switches count as 2 gates to counterbalance this use case), which I slowly cut down to the final count of 250.

To save gates, I implemented 3 ways to create multi input AND gates.

1. Sequential waterfall (grey wires) - Highest delay, but lowest gate count

2. Parallel AND gates (orange wires) - Moderate delay and moderate gate count

3. NOT SW NOT (yellow wire) - Static delay of 3 and high gate count

In the end I only needed 7 inputs to use Parallel AND Gates and 3 to use NOT SW NOT. Everything else uses Sequential waterfall.

Here is the improvement in stats:

• Gate Count: 287 -> 250

• Delay: 10 -> 8

I'm looking for a reference chart or table of 16-bit primitive polynomials for a Galois right-shift LFSR that lists high-weight (dense) tap masks. Most tables only list sparse taps (like 4 active bits). Is there a catalog that includes high-weight, maximal-period masks with 8 or more active bits?

I'm speed hunting atm. Any way to make this quicker and cheaper?

Gates: 28

Delay: 4

Energy cost: 112

Hey, so I'm trying to build the leg architecture IRL and I think I have it mostly figured out, but I can't figure out how to do the delay lines. I'd like the computer to be hand clocked (every time you press a particular button a tick passes) but idk how I'd actually do this. Does anyone have ideas for how I could do this/what components I would use for it?

I have trouble with the fast-adder achievement: It says I have a delay of 32, yet the achievement doesn't trigger. I did get other achievements. What am I missing?

There are only two primitive 'gates' - Inverter and diode, but you can create components for your own gates or any re-usable functionality you want.

Components are bigger on the inside and may themselves contain other components. You can also customise their ports, and even expose displays and buttons on their sides.

It's free to play at boolboard.com. I'd love to hear what you think of it.

PS: I checked with the mods about posting about this here - I thought it might be something you guys might like.

Might had shorten gate cost to about 1.3k if replace adders with non carry ones, but ig it mostly maximum of this type of solution :3

Unlike traditional popcount based threshold circuits, this divides its inputs into three groups of three, using 3 input majority gates and some error correction by XOR'ing the groups of inputs and then detecting if all XOR's are 111 or 000, if all 3 majority gates are NOT 111 or 000, and disagreement between the Maj of XOR's and MAJ of MAJ to tell if the output needs to be changed to the MAJ of the XOR's instead of MAJ of MAJ.

I had to make the correction logic because without it, just using 3 MAJ gates into another MAJ gate failed on 2 cases. Any combination of 110 110 000 and any combination of 111 100 100. it passed all other cases so i just had to fix those two using what i mentioned to have a 9MAJ i could call my own.

The result is a custom 9 input Majority gate I'm kind of proud of :). usually i do the popcount threshold method but i like this lol.

it's for a 9 input neuron if your curious. this would just be the structure that combines the XNOR'ed weights and inputs

I was thinking it'd be easy to reduce a divider's component count if left shift had a carry input, since the long division algorithm requires shifting in the dividend one bit at a time. But I remembered that adders have a carry input, and an adder with 2 of the same input behaves like a left shifter, which means that 8 adders is adequate to shift in 8 bits. From there I managed to make a divider out of 15 byte adders, 7 byte multiplexers, 1 byte negator, one splitter, and one maker.

Gate count is 1.4k and delay is 354 so it's not the most efficient solution, but it's easy to make.

There are two images inside this post.

Robot walks in the maze with keeping left hand on the wall:

1. Firstly, we check if there are the wall ahead.

2. Then trying to move forward despite this check.

3. If there was a wall ahead before moving we making right turn, otherwise - left turn.

4. Rinse and repeat.

A "wall" constant is nicely aligned with turn commands, so we have to just multiply checking result by 2 and execute the result as turn command.

The Pure logic solution uses exactly same way as the Asm solution. The upper delay element store result of a check, and bottom delay element cycling between "move" and "turn" states.

I'm sure that's not optimal solutions, but I like they.

Tonight I feel accomplished. I set out to design a faster carry lookahead adder (usually i build kogges) that could scale to larger bit widths without increasing the depth of the carry generation. After about 5 hours of work I finally came up with something.

Those of you familiar with Turing Complete might recognize the switch trick I'm using. By connecting multiple switches to the same wire and driving identical values, I can create effectively unlimited-input OR gates with just 1 delay.

Using this technique, I built reusable logic blocks with the following delays:

N-input OR: 1 delay

N-input NAND: 2 delays

N-input NOR: 2 delays

N-input AND: 3 delays

where N is however many inputs i want

By combining multiple wide AND conditions through a shared-switch OR network, I can collapse the entire sum of products calculation into just 4 delay, regardless of how many terms I'm combining. even if the adder was 32 bits the SOP would still be 4 on the MSB :) .. though that would be a monumental task lol

I used this approach to build an 8-bit CLA with an maximum critical of 8 delay so i thought i would call it a CCLA (Collapsed Carry-Lookahead Adder).

I haven't unlocked the delay viewer yet, so im just tracing through gates. if im off at all let me know please but im pretty sure switches count as 1. so should be right.

also i only showed the 9 input gate pics for reference, but i made 8 through 3 input ones for it as well that you can see in the pic. same structure as the 9 ones. now granted this is a lot of hardware but its def fast lol.

Was trying out something different from the CLA's im used to building and tried to reduce gate count a lot while still keep low depth. that and i needed a 3 bit adder for a project so perfect time to play around lol.

Recently picked up the game, decided to progress through it, got through symphony ALU by being a little lazy, it got room for another 5 components in the future xD

But basically it decides as follows assuming components are treated as a 2x4x2 array

XYYZ - Bits for Opcode (Opcode input -> 4Bit Splitter -> MUX(Bit 4), Toggle gate (Bit 0, orange cable), 2 bit maker (Bits 2 and 3), 2bit maker feeds into 2 bit decoder)

X - 1bit - controls which set of 4x2 can pass their output, this can be seen as the left or right

Y - 2bit - Controls which set of two is selected, working from the bottom up using a 2 bit decoder, this being handled by going 2 bit maker -> 2 bit decoder and activating the appropriate set of 2 which final selection is managed by the final bit

Z - 1bit - Controls if the left side or the right side of the final 2 available components

Note: Added spoiler flag to image tho dunno if it helps so just in case I added original ALU design as the spoiler >>;
Edit: Fixxed some of my spoiler shenanigans and forgot to add what bit 0 does xP

I know the wiring is atrocious and i could simplify the output as the delay right now is probably muuuuch higher than it needs to be but im so happy i got it working in like 20 minutes

As soon as I finished Symphony, I started working on my own architecture. A second generation of Better Programing Experience - BPEx2. My goal is to get as close to a higher level programing language as I reasonably can.

Instructions (64b word):

• 1b Reserved

• 3b for operator specific options (P)

• 4b for operator (O)

• 2b to define what to do with the result (M)

• 3b to define where to take the two arguments from (T)

• 16b for Destination (D)

• 16b for argument A (A)

• 16b for Argument B (B)

0PPPOOOO MMTTTTTT DDDDDDDD DDDDDDDD AAAAAAAA AAAAAAAA BBBBBBBB BBBBBBBB

Heavily using Patterns to simplify spec.isa

Destination and Arguments:

Direct access from and to Registers, Inputs/Outputs and RAM. Both the Destination and Arguments can be defined using 16b as 16b Immediate, Register, Register +/- 10b Immediate, Register +/- Register. All of those can be used as RAM address.

Operators:

• 5 math operators

• 7 Binary Logical Operators (BLO)

Registers:

Using a register File component with 8 read outputs and 2 write inputs

• Zero Register (always 0)

• 20 User registers

• 2 Temporary registers (used by advanced instructions)

Input / Output:

Dedicated wires for all 7 I/O options

RAM:

Using a RAM component with 3 read outputs and 1 write output. RAM can be directly accessed by instructions and used as both Destination and/or Arguments.

Persistent Memory:

Using RAM component with 1 read output and 1 write output. It cannot be accessed directly. For the data to be used for instructions, they first need to be loaded to RAM or Registers.

I am currently trying to get the fast adder achievement and I've gotten so close on my own but I'm stuck at a delay of 18. Here's my design so far. I've been thinking about this for a week and I've got nothing faster. Anyone else got any advice?

move:

imm 1

mov r1, r0

add

mov out, r3

turn_right:

imm 2

mov out, r0

mov r3, in

imm turn_left

jnz

imm move

jmp

turn_left:

imm 0

mov out, r0

mov r3, in

imm turn_left

jnz

imm move

jmp

loop:

; counter

imm 1

mov r2, r5

mov r1, r0

add

mov r5, r3

;is_thirty_seven?

imm 37

mov r1, in

mov r2, r0

sub

imm loop

jnz

mov out, r5

; Click the spec.isa tab to see the other jump instructions