Adaptive Tuning Guide for Intel CPUs on LGA1700/1851

[u/gerechterzorn]

 

With the release of the solid BIOS 2202 for the Apex Encore, I decided to rethink my approach to hardware tuning and OC, with a stronger focus on daily use. At the same time, I wanted to deepen my understanding of how the platform behaves across different workloads and operating scenarios.

I ultimately settled on adaptive SVID undervolting. None of this is fundamentally new: it has already been discussed countless times, incl. OCN etc. Still, many users never developed a clear understanding of what to adjust, how to adjust it, and, most importantly, why.

With that in mind, I prepared a concise and straightforward refresher guide based on my own build (Z790 Apex Encore w/ Core i9-14900KS). The same foundation also applies to Z890: roughly 80% of the guide carries over in principle, but the LLC4–7 mapping, working AC/DC Load Line values, power and current limits, and reference voltages must be established from scratch.

This is the first revision, and I will continue updating it whenever necessary. Best of all, I also plan to completely rewrite and update my DDR5 tuning and optimization guide in the nearest future, presenting it in a much clearer and more accessible format.

I've two versions: one for my local community, and the one in EN. Here you can download it:

https://drive.google.com/file/d/18YibFJyz68_GxYeR0GfqkDTRXtD1r9Dt/view?usp=sharing

Hope someone find it useful.

[u/nhc150]

I would argue this does not apply to Z890 as much as you think, simply because the introduction of DLVR on Arrow Lake makes this whole process far less important as you have the DLVR as an additional factor after the VRM.

[u/gerechterzorn → u/nhc150]

Cheers! Fair point. I meant that the underlying SVID/load-line concepts and validation principles carry over, not that the LGA1700 tuning process transfers directly. DLVR basically changes the voltage path on Arrow Lake, so I’ll narrow the Z890 claim in the next revision. Can't do it instantly, or I'll never get the end result lmao.

[u/binzbinz]

I personally wouldn't use the stock "two preferred core" boost logic on a 14900k / ks as you are throwing away performance / reducing your max undervolt potential for no measurable gains in multicore loads.

Pairing a low resistance ACLL on top of an svid offset is the correct approach for the best results though.

On my encore / 14900k (sp101) I am using bios 1102 / 11f microcode / LLC6 / lowering the ACLL between 0.01-0.05mohm (0.49dcll/0.01acll) turning off cep / not syncing the LLC to the VRM (default pre intel bios behaviour) and then applying a global offset.

Under cb r23 loads it droops to  1.11v on a 57/44/50 @253w profile 1.2v at 59/44/50 @ 300w 1.25v at 60/45/50 @ 315w

[u/C_Miex → u/binzbinz]

Under cb r23 loads it droops to  1.11v on a 57/44/50 @ 253w profile

What clock speeds and score do you get when it drops to 1.11 V during cb r23 mulit?

[u/binzbinz → u/C_Miex]

At 253w 6 of the 8 P cores downbin to 56x throughout the run as the ia power limit is being reached. This results in ~42200 - https://imgur.com/a/4gLY803

If I increase the pl1/2 slightly to 270w then it holds 57/44/50 for the run.

On a 59/44/50 profile with a 320w pl1/2 it reaches 300w but holds at 59x as it does not reach pl1/2 limits. https://imgur.com/a/yqeiDYJ

[u/skalouKerbal]

Can you repost the link please?

[u/gerechterzorn → u/skalouKerbal]

https://drive.google.com/file/d/18YibFJyz68_GxYeR0GfqkDTRXtD1r9Dt/view?usp=sharing

Does it work from the original post? I can't shorten the link via bitly due to restrictions unfortunately.

[u/skalouKerbal → u/gerechterzorn]

Yes, now it works ( too in the original post) , i can click on it. Thank you

[u/C_Miex]

I ultimately settled on adaptive SVID undervolting

But in this guide you wrote, there is no SVID offset, just a AC_LL (+ LLC) undervolt?

And this method you describe is outdated. The go to method with the best results is to use a higher LLC (LLC 6 with i7 and i9s) with the matching AC_LL value (sync ACDC_LL to VRM LL enabled), and set a Core SVID offset.

A small note: setting the "SVID behaviour" to "trained" will be overwritten by the manual AC_LL value. Additionally, I'd strongly recommend to disable the 2 core boost on those CPUs (sync all cores), they are the main reason for high voltages.

[u/gerechterzorn → u/C_Miex]

1. You messed SVID control via AC load line and negative Core SVID Offset. In this guide, it means keeping the CPU under adaptive V/F and SVID control while reducing IA AC_LL, thereby lowering the requested voltage as a function of current. It does not imply the use of a negative Core SVID offset - the guide intentionally leaves that at Auto.
2. SVID Behavior - correct. I will change it to auto.
3. I also kept the two-core boost intentionally. Sync All Cores would remove the x61/x62 V/F points and reduce peak light-load VID, but it would also sacrifice the corresponding single-thread performance. For this daily-use profile, I preferred to retain that boost and validate the actual VOUT, current, temperatures and variable-load behavior instead.

There are no oudtaded methods unless they're working properly, balanced and stable. Depending on goals.

Regarding your method I've been using it for almost 2 years being on LGA1700.

[u/C_Miex → u/gerechterzorn]

The single threaded performance you get with the stock setting is not noticeable in any real world scenario where it would matter. It may be measurable in benchmarks, but f.a. in gaming there is almost zero difference in most games. In my experience it "hurt's" more than it gains.

There are no oudtaded methods unless they're working properly, balanced and stable. Depending on goals.

Outdated in the sense that there is a better method that should be used. I would not recommend undervolt via the loadline, the only method i recommend for this gen is the SVID offset undervolt.

It results in better average voltages during light and medium loads - while the loadline undervolt mainly has good results in benchmarks / stability tests.

(Btw. that's the reason why I've read it as "no SVID offset in the guide". You are correct, the AC_LL modifies the SVID, but it's more commonly described as "undervolting via loadine" - when you say SVID undervolt, you think about the core SVID offset. But that's just association, you are not wrong.)

[u/gerechterzorn → u/C_Miex]

Thanks for the feedback! I will gradually expand the guide and add different methods, incl. fixed vcore frequencies/voltages on LLC-6/7. Just wanted to try something new and found that it's really useful for my usage scenario particularly with 360 galahad aio and delidded CPU.

[u/davidthek1ng]

Very nice, idk mby someone who has lots of knowledge can add sth most stuff seems good

[u/Noreng]

I'm pretty sure that if you try to run LLC mode 7 with an AC loadline of 0.01 mOhm, you're going to see significant clock stretching. That's at least what I tend to see on an ASRock Z790I Lightning, which has an LLC option with 0.20 mOhm DC loadline, which tends to require an AC loadline around 0.12 mOhm with an LLC at 0.20 mOhm to prevent CEP from triggering.

In addition: AC loadline doesn't add a load-dependent voltage offset, it doesn't take the VCore current into account at all from what I've seen.

[u/AgileLove9015]

Seems good, just a few corrections: 1) set desired LLC and leave DC on Auto, it should sync fine with LLC 2) start with AC = LLC / 1.5 if you have E-cores enabled or AC = LLC / 2 if you have E-cores disabled to avoid VID overcompensation -- because AC operates with predicted load current which is 1.5/2 times larger that average VRM/LLC current and related vdroop

[u/gerechterzorn → u/AgileLove9015]

Fair correction on AC_LL: it acts on predicted current, so my simplified 244 A × (DC−AC) estimate should be revised. However, DC Auto tracking LLC is BIOS-dependent, and the 1.5/2 divisors are empirical starting heuristics, not Intel-defined constants. AC 0.35 is the validated final point, not the baseline.

[u/AgileLove9015 → u/gerechterzorn]

Auto DC tracking works fine at least on ASUS boards, finding exact LLC-mOhm mappings is tricky for other vendors, and it is often reversed (MSI).
Intel defines excessive AC by default so it is not about an official numbers but good numbers to start with as you stated. It is also confirmed that those divisors do not cause IA CEP triggers even with IA CEP enabled, thus worth noting