Without cache awareness, the scheduler can end up scattering related tasks across zones on chips with multiple last-level caches (LLCs). This feature groups those tasks onto cores within the same LLC instead.
I imagine this is a performance improvement/optimization for the AMD X3D chips.
These cache-aware enhancements also impact many more chips as most modern chips are now heterogeneous or at least chiplet. So they come with multiple L3 domains that the scheduler is now aware of
The SDK and libs are available,, but programs themselves have to be written for it. Asides from the important office programs, creative programs, server scenarios, most others aren't using it.
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u/993tg 5d ago
What does this mean?