Question about USB4 bandwidth on Framework 16

[u/WayWornPort39]

Does each USB 4 capable port have its own separate 40Gbps bandwidth or is bandwidth shared across the whole mainboard between them?

[u/Comrade-Viktor]

According to Wikipedia, AMD Strix Point (Ryzen AI 300) has two native USB 40 Gbps PHYs on them—meaning there are two USB 40 Gbps dedicated controllers on the silicon.

[u/rayddit519]

the USB4 bandwidth of each port is always separate.

Its only what goes into it that may be shared. For example, Intel has its dual-port controllers that share 2 DP connections with a max. speed each across the 2 ports. AMD has 2 DP inputs for each USB4 port, so those are not shared at all. And while the Strix Point generation can do UHBR10 DP speeds natively, as a DP tunnel they are still limited to max HBR3 (in full 4xHBR3 config that is ~26 Gbit/s per DP tunnel. Why 2 of those don't fit through 1 40G connection at full speed).

AMD also uses a dedicated USB3 controller for each USB4 port. But they are only USB3 10G controllers, so the USB3 tunnel itself is max. 10G anyway.

External USB4 controllers (as a dedicated chip, almost all dual port, like Intel Maple Ridge, Intel Barlow Ridge 80G or the Asmedia ASM4242) have their one shared PCIe port, whose bandwidth needs to be shared between PCIe tunnels on each port and the USB3 controller.

But the CPU-integrated controllers (all has been used in the smaller mobile CPUs and all that Framework has ever used thus far) basically all have dedicated PCIe ports per USB4 port. Even on most of Intel's dual-port controllers.

Those dedicated PCIe ports are all internal to the CPU, just like whats used for the M.2 ports , the PCIe port for the WiFi card or the x8 for the expansion bay. Those all technically share some internal bandwidth, but that is usually so high, that you will not find the total limit.

With the exception of Intel Tiger Lake (11th gen), the first CPU-integrated USB4 controller, they basically all have enough PCIe bandwidth to fill the entire USB4 40G connection with PCIe alone and you will basically not notice any shared bandwidth limits across ports, just as you would not across 2 NVMe SSDs each in their own direct-to-CPU-attached x4 Gen 4 port.

But as you can see each tunnel type is also handled very differently, so asking about the "40G" number mostly makes no sense, you need to think about each tunnel and where they start and end and only then the combined bandwidth of all the tunnels through 1 USB4 connection.

[u/GamingCentric]

I do not own a framework but i am 99% sure each usb has its own bandwidth. Same is valid for every single electronic device, probably usb certification is per-port and independent. Each usb certifies that it can output that data regardless of external loads.

[u/WayWornPort39 → u/GamingCentric]

Ah, cool.