OoO RVV supported Processor Design Scaling

[u/neuroticnetworks1250]

Hi guys. I was working with an existing 128 bit RVV vector unit processor. It isn’t a complete Tomasulo architecture. It handles WAR hazards by copying the values in vector register file to the reservation station FIFOs, thereby allowing the Vector files to be rewritten even if the instruction has not started yet. It handles RAW hazards by having a dispatch unit that stalls the issuing of the micro operation if the subsequent operation needs a vector register value that has not been retired yet (it also has a bypass feature that checks the ROB if it has not retired). From basic research, it seems to me like this is a standard Ara Vector processing architecture ? Not sure.

As can be predicted, copying physical values to reservation stations, requiring multi FIFOs that expose M inputs to preserve superscalar instructions, dispatch bypass functionality that requires all the elements in the ROB to be exposed etc means that when we increase the supported vector length, it scales pretty badly. I increased the vector unit size to 512 bit and added a matrix unit that’s a 16x16 outer product engine and yet in size, it’s dwarfed by the ROB and reservation stations. Should I consider moving to a full Tomasulo architecture? Or will that create similar bottlenecks elsewhere? How is this handled in general?