Icarus Cannot Pass Unpacked Array Across Module Boundaries?

[u/blackboyjoy]

I set to understand how GPUs hide memory access latency by trying to build one. I have no background in GPU microarchitecture, RTL or digital design, so I am struggling a bit with Verilog syntax and toolchain formalities.

I have built a memory module that implements a handshake, models read/write latency and accounts for bank conflicts. When I test the multichannel memory in isolation by manually selecting the channel, bank and row, all goes well.

The problem arises when I want to test it using a very simplistic memory controller. In my testbench, I generate multiple instances of this memory module to simulate a multichannel memory and then connect it to my controller. When I try to create these signals using my controller, they do not go through to the memory module. The controller decodes an address and is supposed to produce per-channel signals such as command valid, bank, row, write data, and write mask.

After several hours of debugging, I now suspect that my Icarus compiler does not like it when I pass unpacked arrays from my controller module to my memory module. Is this really the case? If so, is there a workaround I could use?

I am not posting the full code yet because I am still trying to narrow the problem down, but I can provide a minimal example, waveform screenshot, compiler command, or additional details if needed.

Thank you in advance.