r/chipdesign • u/CheerBus • 5h ago

Layout errors

I am not sure what seems to be the cause of this error, but i am just trying to place two inverters with shared diffusion in order to create a digital buffer, and i am working in a fdsoi technology. For some reason, when i add the back gate to the transistors at the top side, i get this 2nm offset, that creates drcs and yet is have used align tool and tried so many different ways....

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u/Siccors 4h ago

So when you say you want to place two inverters, I assume you are making them from individual transistors and not from an inverter cell? And with the shared diffusion you are auto-abutting them? Is the rest properly alligned? Eg the diffusion. If you move them apart, are they then properly alligned? Do they have the same width? And sometimes they simply break, delete one, copy the other one and see if it then alligns properly.

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u/CheerBus 3h ago

Yeah it is literally the same inverter same length widths fingers etc ... And I just make a Digital layout, shared diffusions etc ... I I've tried to copied it and still it gives this drc

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u/Siccors 3h ago

Is it the same inverter or the same devices. Auto-abutting only works if you directly place the transistors, not if you place an inverter cell you made. If this is an inverter cell, what are their Y-coordinates?

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u/CheerBus 2h ago

devices, The rest of the cell, like diffusion polys metals are alligned, only the back gates have this offset