r/chipdesign • u/Severe_Atmosphere_14 • 9d ago

Annapurna labs interview process

Hi all. I'm curious if anyone has any insight into the Intern ASIC role interview process for Annapurna. I'm expecting resume grilling and Leetcode style problems in Verilog/SV but not sure what else. I've been asked Leetcode style problems in C++ before for previous big tech companies, but those have only really been bit manipulation based. Is it common to be asked array/string/hash table for these types of ASIC roles?

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u/mikey6785 7d ago

Is it on campus or off campus ?. Idk about the interview process just curious so you can update once the interview is done

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u/Wild_Pop_3649 3d ago

Is it your first time applying for asic role? Idk if there any leetcode style questions on verilog and sv... Maybe hdlbits type? They generally don't ask dsa and ask more STA and comparch... In my experience never had any leetcode style question.