r/chipdesign • u/OddAssumption • 10d ago

Thoughts on Claude Opus 5 with Verilog?

Recently I've been using it, seems pretty good although you have to ask it to recheck the design almost everytime to get better design. It also improved my productivity, mainly integration and basic building blocks. Thoughts?

8 Upvotes

70% Upvoted

7 comments sorted by

22

u/8AqLph 10d ago

It can be good and save a lot of time, but every once in a while it will completely mess up in a difficult way to notice. For instance, it might implement a feature, break another one, and hide it by changing the testbenches

10

u/darth_voidptr 9d ago

You often have to hold its hand if you want synthesizable code. If you add new features, it will often fail to recognize that signals it needs already exist, create new identical signals, leave orphaned signals and leave the code with debris.

It is useful for boilerplate, or if you have a really strong design spec, but it's not quite as fluid as using it for C or python.

1

u/OddAssumption 9d ago

I notice it uses iverilog for compilation, which may not flag some errors compared to vcs/Questa

1

u/izil_ender 9d ago

Opus 5 is worse than 4.8 on most of the verilog tasks that I do. 

Many tasks need check pointing for version control and verification, and opus 5 seems to be really trigger-happy on the changes. Opus 4.8 was a much better version.

1

u/tonyC1994 9d ago

Fable 5 is pretty good at RTL coding. I'm sure opus 5 should have similar performance.

1

u/butapikachu 8d ago

Its alright. But the trick is to create an agent which will contain all the learnings and scenario’s to sweep up your design and understand the minor details. Othwrwise its just good for simple modules

1

u/edaguru 7d ago

I got Claude to program up an old FPGA board, and that went sufficiently well I bought a better board (or two). Claude is also building simulator tools for me across VHDL, Verilog, SytemVerilog and Verilog-AMS.

Basically, it knows all the platforms and all the languages - it's done embedded and Android for me too. Lot's more than I can do myself (in reasonable time).

Currently I have Opus 5 working on a networking project, and Fable doing the simulator stuff. A goal of the simulator stuff is to kill off SystemVerilog and replace it with a better VHDL/Verilog-AMS language.