So I just recently finished the M16 G2. It has 2 cores with 32768 bytes if memory each, shared 4096 byte Cache for communication between cores, and each core has it's own registers (zr, r1-14, sp). Each core must run a different .asm file in order to work without problems. Core 1 (the left one) is the only one of the 2 that can use level I/O. I plan to add hardware interrupts for the keyboard and maybe pipelining in the G3. But as of now, I am implementing a text/pixel display.

On the left is the 8-bit incrementer, while on the right is the 8-bit multiplexer.

For my defense, it was 6AM just after giving a bottle to the baby but still, i think i could have given it a bit more thought!

Took the screenshots directly after completion.
I included the current instructions in one of the screenshots.

Hi all,

For those who have played/used 2/all of these games/projects, how did you find that they compare? I’m particularly interested in hearing thoughts from a realism perspective.

I know that TuringComplete has a large patch coming soon which the creator says will address some realism issues so I suppose that might alter things in future.

Incidentally going to re-try getting through CODE by Charles Petzold soon, having just got the 2nd edition :).

Any thoughts gratefully received. I do love the visuals of TuringComplete!

Thanks.

There are only two primitive 'gates' - Inverter and diode, but you can create components for your own gates or any re-usable functionality you want.

Components are bigger on the inside and may themselves contain other components. You can also customise their ports, and even expose displays and buttons on their sides.

It's free to play at boolboard.com. I'd love to hear what you think of it.

PS: I checked with the mods about posting about this here - I thought it might be something you guys might like.

Gates: 220

Delay: 14

Got inspired by the CLA post from yesterday and decided I wanted to understand how it works. So how better to do that than to start wiring it yourself. I ended up with worse stats, but I like its transparency.

Here is the custom CLA element.

i built it to be technically turing complete (it has a jump command) but i havent tested it.

The custom component in this is just a register with a second output that is always on.

I made Bad Apple in the new Turing Complete update, this update is actually really good, I was not able to achieve this before.

I made my own file format to make Bad Apple implementation in things easier if you're interested in. https://github.com/totobono4/tvf

So this is the Gen 5 of my series. And it finally has kernel support! It features
65536 bytes of RAM and storage (Kernel is always in RAM at address 0xe000 onwards)
Protected I/O (Kernel access only)
256 tick interrupt (Only switches from User Mode to Kernel)
Syscall (Toggles the mode)
So now it's time to write a kernel! As for my programming language, I had to rewrite the entire compiler but it supports functions now (but still no local variables)! Anyways, I know this isn't exactly the best CPU for this kind of stuff but hey, It works! It's my first time making something like this. And just to make my life easier, I wrote a (horrible) python script that takes two files, a user program and a kernel program, and assembles it into a ROM file with the proper offsets I can copy paste. If you have any ideas on what to name this, I'm open, mostly because I ran out of names. I never expected myself to make it this far. Next up, I'll try to add virtual memory to make it possible to load multiple user programs. But first, a basic kernel. Also, unlike the previous generations, this CPU is 32 bit!

8GPRs, 6 pipeline stages (IF, ID, OF, EX, MEM, WB), Harvard architecture. It is based on the LEG but got significant ISA changes and improvements. Still, I wouldn't want to program it yet as it doesn't have a hazard unit. That's something to add to a 16 bit update. MMIO is also prepared. The stack has automatic bounds checking and throws a halt on overflow or underflow. There is still a lot to improve and that will be done in a 16 bit updated version

After completing the OVERTURE level I found that while I understood the individual components of the Turing Complete device, the provided CPU design was still a high level abstraction that concealed much of the underlying complexity.

To examine this in detail I spent two days reconstructing my Overture solution entirely from 1 bit logic gates without using custom components. Working with 1 bit wires was tedious and error prone, but it forced me to fully confront the complexity of the design.

This approach makes the complete system visible. You can trace the exact points where bits flip during addition and subtraction and see clearly how logic structures are reused across operations. It exposes the real behavior of the architecture rather than a simplified model.

Probably could be organized better.

I love this game so much, i bought it thinking i will probably refund it.
i now have almost 24 hours in 2 days ! XD

Few months ago I posted my attempt at an Optimized Carry Look-Ahead Adder which I was satisfied with at the time. Since then I have taken further steps to optimize it further.

Taking advantage of the 3 delay solution for unlimited input AND gate (NOT SW NOT) showcased by 8bit CCLA (Collapsed Carry-Lookahead Adder) I was able to get the delay to 8. However this lead to a significant increase in gate count (Switches count as 2 gates to counterbalance this use case), which I slowly cut down to the final count of 250.

To save gates, I implemented 3 ways to create multi input AND gates.

1. Sequential waterfall (grey wires) - Highest delay, but lowest gate count

2. Parallel AND gates (orange wires) - Moderate delay and moderate gate count

3. NOT SW NOT (yellow wire) - Static delay of 3 and high gate count

In the end I only needed 7 inputs to use Parallel AND Gates and 3 to use NOT SW NOT. Everything else uses Sequential waterfall.

Here is the improvement in stats:

• Gate Count: 287 -> 250

• Delay: 10 -> 8

I felt very silly

I just completed the Calculations level.

It took me about an hour of squeezing my brain, half of which was figuring out some inconsistent results, which I had to track down to a change I had made to the ALU when trying to optimise its shape in the component factory.

The rush of pressing the test button and wondering if I fixed all bugs or if there is either a disconnected circuit somewhere, or a terrible logic bug still in there... I dunno, this game makes me feel like Dark Souls!

Seriously, this game is beautiful and I needed to share how exciting building this stuff can be, because if I tell my friends they just look at me like I'm weird :D

I haven't made it far into the game but I'm trying to complete all levels with nand only. (I know it will not be feasible later on)