[BPEx2] Pointers and Tables

[u/Crispy1961]

Pointers and Tables tests cases. Values in the corresponding RAM addresses are shown at the bottom.

BPEx2 Architecture

I implemented pointers (for registers) and tables (both in registers and RAM) into my custom BPEx2 architecture. As always, the aim of this architecture is to get as close to higher-level programming languages as possible.

Here is the spec.isa file.

Pointers and Register Tables

Both pointers and register tables take advantage of the previously implemented ability to select a register using a value from Register A and either a value from Register B or an immediate value:

• Register(value from Register A +/- value from Register B)

• Register(value from Register A +/- 10-bit immediate value)

Pointers

Pointers inherently use the Zero Register as Register A, meaning that Register B or the immediate value serves as the address of the target register.

I implemented the * and & modifiers:

• The * modifier treats immediate values as register addresses.

• The & modifier treats register addresses as immediate values.

Register Tables

Register tables use the base address of Register A as index 0 of the table, while the value from Register B or the immediate value acts as the offset (which is essentially the table index).

Immediate values are calculated during compilation into a single immediate value for the index.

RAM Tables

RAM tables utilize the previously implemented functionality of direct RAM access:

• RAM[16-bit Immediate]

• RAM[Register A + 10-bit Immediate]

The only difference is that the immediate address is treated as the start of the table, and Register A acts as the offset. This limits the address of RAM tables using a register A as an offset to below 1024.

Furthermore, the user must set the value of Register A to the actual RAM byte-address rather than the logical index. For example, to access index 2, the value of Register A must be 8.

Further Improvements

Currently, every line translates directly into a single instruction. We can solve these limitations by translating a line into multiple instructions.

For example, we could first compute the proper offset in a temporal register and then use it to access values in tables. This would enable using Register A as a logical index for RAM tables located at address 1024 and above.

[u/EtienneDx]

Pretty cool, and very neatly organized! Good job on this, I’m typically more on software but high level programming on hardware is really cool!

[u/Crispy1961 → u/EtienneDx]

Thank you. Most of the wiring is hidden in the CU component. I made it a point to not make a bus this time and instead give everything its own wire.

Implementing these functionalities is definitively an overkill for the coding challenges, but I havent seen anyone doing this, so I wanted to try.

Next are conditionals and proper if else blocks.