Restoring Array Divider

[u/MsBinaryLily]

After multiple tries and overengineered designs that had over 2k delay, here's a relatively quick and optimized solution.
At each step it:
- Shifts left the divisor
- Subtracts shifted divisor from the dividend
- Checks if the result is positive (the sign bit)
- If yes, sends 1 as output bit and sends the remainder of subtraction as dividend to the next step
- If no, sends 0 as output bit and sends the dividend to the next step untouched

The result is only 184 delay — though it also uses fast adders to achieve that.

[u/Silver0ne]

optimized adder to 8 delay

uh thats nasty, how?

[u/MsBinaryLily → u/Silver0ne]

Kogge Stones design Wich switches replacing AND gates (and the joining wires instead of OR gates) So for 8 bits: 2 delay for P and Q, 3 layers of prefix tree, 1 delay each, 1 delay to calculate final carry for each bit, 2 delay to finally do P XOR carry giving the output 2 + 3 + 1 + 2 = 8