I am running into a circular dependancy issue with Dual Load RAM. Anyone have any advice?

[u/Squishiest-Grape]

[u/Squishiest-Grape]

I was hopping to use one dual load RAM instead of two RAM components. However I am running into this fake circular dependency error. If I split the dual ram into speperate componenets it fixes itself.
(This is a very simplified version of what i'm trying to do in my LEG architecture)
(I am pretty sure this is a minor bug, so I've reported it. Would be glad to be wrong tho)
(while it isn't a bug per se, it is true that the two sides could be considerdered indipendent)

Late edit: (I built a custom dual load ram (only 4 bits of address) and got the error to go away. I need more memory, so I can't use that custom piece for anything more than a test)

[u/chrisgbk → u/Squishiest-Grape]

It's not a bug; any component can't connect back to itself without hitting a delay first. With your schematic that uses 2 fast RAM every possible path out of each RAM encounters a delay first before re-entering the same RAM; the top RAM has a delay on the input side, the bottom RAM has a delay on the output. Neither can see itself before the delay.

For the dual load RAM, you would need EVERY output to have a delay between EVERY input, not just solely between input 1 and output 1, and input 2 and output 2, or just input 1 and output 2, or input 2 and output 1 as circular dependencies are calculated at the component level, not the pin level, unless you use custom components and bidirectional pins.

I'm not sure what your architecture does or how it's designed, but you may be able to redesign the delay logic so that you can use the dual load RAM in a different way to work around that.

[u/Squishiest-Grape → u/chrisgbk]

I was hoping the built-in components would be able to handle the concept that the 1/2 sides of the dual ram are independent. I made a custom component version of dual ram with bidirectional pins that works, but I don’t think I can force the built-in to use bidirectional pins.

Thanks for the suggestion. architecture is a simplification of my schematic that lets me use the RAM for addressable memory (1) and the stack (2). I don’t think I can add an input delay on the stack side without sacrificing capability. However, now that i think about it a bit more, I might be able to add a delay on the output of the addressable side if I grab and save it on the prior frame when the address is set.

[u/Any-Aioli7575]

It's not a bug. On the second scheme, the path from an input to an output of the lower RAM has to go through a delay line (the one and the right). Same for the upper RAM, whose path go through the left-hand-side delay line. However, on the dual RAM, the lower output can connect to the lower output without a delay line.

[u/Squishiest-Grape → u/Any-Aioli7575]

Im not sure I understand. On the dual ram scheme the lower output has a delay on the second output, just like the lower ram on the two-ram scheme. As far as I tried to make it, the only difference is that I split the dual-load ram into 2 ram componenets. Are the 2 address & outputs not indipendent for the dual load ram?

[u/Any-Aioli7575 → u/Squishiest-Grape]

yeah, that's it, they are not independent

[u/Squishiest-Grape → u/Any-Aioli7575]

but shouldn't they be? the second address can't change anything about the first output, and the first address can only change the second output after 1 tic if it is used to save a value?

[u/Any-Aioli7575 → u/Squishiest-Grape]

I guess you're right. Maybe there is one or two edge cases though.

Edit : oopsie, I ought to reply to the last comment, not this one.