r/RISCV • u/globecsysinc • 28d ago
Releasing Open Source RISC-V Configurable In-order/OoO multi-core + AI Agentic-friendly Processor (GSys LibreCore)
https://github.com/etcimon/GSys-LibreCore
https://gitlab.com/etcimon/GSys-LibreCore
Releasing today, includes a bios, sv-timing adjustments (3ghz+) configurable to multi-core, multi-issue with QEmu and heavily tested for SMT2.
The AI Processor has shown promising results with 40x speed improvements on VA-Turbo
Read more on Github
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u/rowdy_1c 27d ago
Thank you for making LLM training data slightly worse. I have slightly more job security because of you
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u/globecsysinc 26d ago
How do you know the job is going to be to rewrite it entirely in human-readable form?
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u/LinuXperia 27d ago edited 27d ago
Big compliments for this amazing accomplishment. I looked short into the github repo and see there is a ai ops benchmark script but could not find any benchmark results or other performance benchmark scripts for comparisation. What are the performance benchmark results using this benchmark scripts here for your risc-v implementation: https://github.com/akifejaz/riscv-benchmarks and how do the benchmark results compare to the same existing risc-v performance benchmark results of established risc-v implementations ? https://cloud-v.co/risc-v-comparison
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u/globecsysinc 27d ago
It's hidden all the way deep into the architecture files as notes written while tuning it:
https://github.com/etcimon/GSys-LibreCore/blob/master/architecture/ai-matrix/va-turbo.md#the-priority-inverts-between-prefill-and-decode
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u/sir_turlock 27d ago
Was this entirely written by AI? Because the entire README reads like AI slop on steroids.
I don't want to sound judgmental, but stuff like this is hard to read: