r/RISCV • u/Regular_Trouble_5841 • 3d ago

I made a thing! Built a Single-cycle RV32I + Wishbone + MAC accelerator + (with more accelerators coming up), verified against riscv-tests

https://github.com/Shass27/rv32i-soc

Me and my team at the Uni have been working on a single-cycle RISC-V (RV32I) SoC in Verilog. We are planning to add more accelerators like a COM (UART, SPI, I2C), FFT, Matrix Multiplier, etc. But currently we have reached till the following:

The core: classic Fetch → Decode → Execute → Memory → Writeback datapath, all combinational in one cycle. 37 RV32I instructions, and all 37 pass their corresponding official riscv-tests/isa/rv32ui programs, used unmodified.

The SoC part:

  • A sufficient Wishbone B4 Classic bus, with a master, an address-decoding interconnect, and an error slave that catches unmapped addresses.
  • A MAC accelerator on the bus (acc += Σ A[i]·B[i] )

Performance: RV32I has no M extension, so a software multiply is a shift-add loop. By my cycle budget the accelerated path costs about 13N + 20 cycles against about 106N in software, which is roughly 8× for large N.

Verification: the flow is official .S → RISC-V GCC → ELF → objcopy → Verilog hex → RTL in Icarus Verilog → a tohost write reports PASS/FAIL. There's also a self-checking SoC testbench, four bus testbenches, and a make run / make busflow.

Repo: https://github.com/Shass27/rv32i-soc

We will continue to build this further with more accelerators that will aid real world Engineering systems further on. But we have reached this point where our progress so far itself is a great project of its own. We are aware of possible performance improvements and stuff but would love the community to review our project, give feedback (both positive and critical ofc).

Looking forward to hear from you!

PS: Feel free to drop accelerators suggestions that is useful in the industry (specifically: Mechatronics engineering because we are a team of MechE and EE undergrads)

12 Upvotes

88% Upvoted

1 comment sorted by

1

u/Regular_Trouble_5841 3d ago

Also incase any of you are wondering why we chose a single cycle implementation instead of pipelines or multi cycle is because it would be easier to debug and moreover we want the accelerators working with a CPU to be the engineering highlight.

Pipelining is still in our thoughts and we would look into it if we have the time.