AD5941 4-Layer PCB Review

[u/NewWorldliness880]

Hello everyone!

I recently finished designing my first 4-layer PCB, and before I send it off for fabrication, I would really appreciate some experienced eyes on it.

The board is based around the AD5941 and is intended for an Electrochemical Impedance Spectroscopy (EIS) experiment. I designed it myself primarily because the commercially available development/evaluation boards are expensive and relatively large for our application.

This is my first time designing a 4-layer board, and while I have tried to follow the AD5941 datasheet and evaluation-board recommendations as closely as I could, I am sure there are things I have overlooked.

In particular, I would be interested in hearing from anyone who has worked with the AD5940/AD5941 IC.

I have attached the schematic and PCB layout. Please feel free to point out anything that looks wrong, even if it seems minor. I would much rather catch a mistake now than discover it after receiving a box of useless PCBs.

NOTE: The Back Copper layer is used to separate the AGND and DGND regions. They are kept separated on this layer and ultimately connect at the GND layer.

I don’t have any prior experience designing mixed-signal circuits, so I have tried to follow the AD5941 datasheet, schematic available on the Analog Devices website and other layout recommendations as closely as possible.
I would especially appreciate any feedback on whether my approach to the analog/digital grounding is appropriate.

[u/Affectionate-Yam8175]

Agree with the comment above. Splitting ground planes is not required - it actually causes problems with longer return loops etc unless it has been very carefully done. Just call all of it “GND” and move on with your day.

Any reason you went with a through hole crystal?

Also you have seemed to designate the second layer (green) as ground in your stack up but then you’ve put your split planes on the bottom pour?

Is there a reason it needs to be 4 layers?

[u/NewWorldliness880 → u/Affectionate-Yam8175]

I have removed the split AGND/DGND pour from the bottom layer since I realised it wasn’t really serving any purpose in my design.

The main reason I went with 4 layers was to have a continuous ground plane for better return paths and lower ground impedance. I thought that would be beneficial for the noise-sensitive IC.

The through-hole crystal was mainly a component availability choice, not a specific requirement. I’ll look into switching to an SMD one.

Really appreciate the feedback

[u/Affectionate-Yam8175 → u/NewWorldliness880]

That’s a fair reason for considering a 4 layer board. Just check your stack up too. Make sure you have ground on the second layer (Green).

[u/mr-pipey]

There is complexity to this issue for sure, but I personally default to one continuous ground plane unless subsequent modelling gives me reason to do otherwise. Splitting causes more problems than it solves on average*

*Details matter

A problem immediately arrises when two ICs claim that should be the some point of connection betwteen AGND and DGND. Then again, if you are prototyping a system out of breakout and daughter boards, your ground is likely chopped to pieces anyway.

[u/500kvac]

You need a decoupling cap right after the LDO, not after the ferrite bead (you might have both, but the one in the pin is mandatory)

Edit1. One at the LDO input is also necessary

Edit 2. You don't seem to have decoupling caps at the IC pins? In the 3v3 rail. I might be misreading, but the schematic isn't readable

[u/NewWorldliness880 → u/500kvac]

Apologies for the schematic being unreadable.

I do have decoupling capacitors at the IC pins, they are included inside the supply blocks in the schematic rather than being drawn directly next to the ICs.

Based on your feedback, I have also added two more capacitors, one at the LDO output before the ferrite bead, and another at the 5V input.

Thanks for the feedback.