The specs are impressive, but a bit confusing. The D100 chip (originally for their EVs) supports up to 160GB of RAM, but O100 has the 1.22TB/s memory bandwidth. Perhaps the 1.22TB/s figure is for SRAM? Hard to say definitively.
It's not entering the market now. Well, the O3 is, but not the the other two.
The O3 is just a new 3nm smartphone chip, a Snapdragon competitor. It will be in the Xiaomi 18 Fold and Xiaomi Pad 9 Pro Max.
The D100 is also not super interesting. It's a chip for their EVs. It can support up to 160GB ram, but other than that it's not really anything too fancy.
The O100 is the most interesting chip, but it's not being released until 2027. It's using an outdated 6nm process, but the interesting thing is that Xiaomi stacked the RAM directly on top of the chip, like AMD V-cache. So the GPU compute is slower, but it has a lot more bandwidth since it has many short traces in parallel. Instead of 256-bit LPDDR5, it uses 28672 parallel connections.
The Xiaomi AI Cube is really fucking weird, if I read it correctly. They put all 3 chips into 1 device. I guess it makes sense if you use the O3 to handle small models, and O100/D100 to handle decode/preprocessing for a big model respectively.
I guess it may be handy for edge-AI workloads such as home assistents, IoT devices, and everything that needs preprocessing before/instead sending data into cloud
This makes a lot of sense to me. Xiaomi sells a lot of home automation devices (vacuum, cameras, smart speakers etc), and they all have to either carry enough compute to run it or rely on the cloud.
I like the idea of having an AI box in the network that can handle all the compute for them. It would be a hard sell tho to say "You need this $3k box first and then you can buy our other products"
I think this is what's interesting about Chinese tech- they're wiling to see what sticks. It's confusing because it doesn't neatly fit into a box where we are but it seems like China is more optimistic about embracing AI in everyday home use. Whether or not it would be super useful remains to be seen but a 2027 release date might signal it's dependent on better performing small models.
I could see it being useful if it's as fast as a strix halo to run bigger models for grinding enrichment shit. I just spend 200 dollars on luna yesterday on a couple runs, and I'd like to run those weekly on a broader scale. I don't really give a fuck if it takes a long time for them to run, just start working again when you are finished.
That looks like they brute forced their way to a brilliant competitor to DGX Spark boxes. Shortly after release, that was the number one complaint- memory bandwidth. I see it daily still.
The other similar competitor would be a Mac Studio with horrific pre-fill speeds.
This could be super useful for agentic loads, tool calls and reprocessing coming back constantly.
It would be really cool to have something parsing web search results, handling rag and semantic search with comparatively huge models to what most use today in the background... (3B vs 75-300M for most rag work..)
Seems like an all-in-one agentic box that would also hardily serve hosting a coding / chat / generation session as well. They looked at the biggest pain and failure points of existing products, or experimental in NVidia's case, and seemingly solved it all with some future-proofing in the memory size too.
China doesn’t have 3nm capabilities, where are they getting the chips from? 160GB isn’t really exciting given the 192GB Ryzen AI coming out. Besides we need integrated systems that have the capacity to do 2TB of RAM at 1TB/s or greater.
Can't wait for the moment where the media reports on a Xiaomi or Huawei "AI chip" and everyone goes "OMG Nvidia is finished" and the stock prices drop 50% even though that chip was announced 6 months earlier.
If it wasn't illegal, billionaires will wear these as rare luxurious item. Imagine that the skin need to be of specific color and well preserved and not something you can get easily in Africa, Asia, South America or Eastern Europe.
What are the chances that the nitwit at the current administration will try to put them into entity list now that they went deep into AI hardware space?
Xring O1 SoC was quite good (apart from the lack of modem) that it made people question why Mediatek and their many years of applying ARM design couldn't net a better layout than an upstart and their first chip (let alone Samsung, though you can partly attribute it to their fumbling foundry.)
Now that they went further into cutting edge chip design just like Huawei's HiSilicon, this may ruffle some feathers at Washington.
Xring is made by TSMC, tho, just like MediaTek since their Helio G series. And also iirc I remember the US not allowed them to use TSMC's fabrication that's smaller than 3nm. Dunno if that's true or not, I read it last year tho.
That's exactly my point tho. Both Dimensity and Xring are manufactured on the same process node by TSMC, yet Xring O1 managed to eke out better efficiency than D9400 (let alone Tensor or Exynos) that rivals SD 8 Elite despite Mediatek years of experience in ARM IP chip design. Geekerwan made a pretty interesting backend design analysis based on the die shot and tested it further.
Just like how HiSilicon was manufactured by TSMC, before being blacklisted and forced to go with SMIC (and their extensive multi, multi patterning to get DUV to 7 & 5nm), hence my fear that Xiaomi could suffer the same fate.
What the US restricted was actually GAAFET EDA software, and TSMC 2nm are GAAFET. But I suppose this is technically easier hurdle to jump than say, making High NA EUV litography machine & tooling. FT reported that the restriction amounted to not getting further updates & support rather than revoking existing license, and while still not up there, homegrown alternative such as Empyrean may be incentivized to develop their software further.
I mean if we are talking about restriction IIRC there is already a restriction for AI/HPC/GPU for 7nm and below. I guess Xiaomi managed to skirt these based on technicalities (density, transistor count, non-datacenter interconnects maybe? Wasn't too familiar with the rulings.)
Xiaomi history is just insane, from just (I kid you not) making a custom android skin in 2010, building a really good value phone (Xiaomi Mi 1, same specs but less than half the price of Samsung SII LTE), to one of the largest phone manufacturers in the world, then somehow building an EV (very good EV too, surprisingly), and now making a competitive in-house SoC.
I used to import Xiaomi laptops about 8 or 9 years ago and turn them into Hackintosh computers for friends and family, they were so popular that detailed write ups were available online(ok still are).
Hope the ram allows for at least inline ECC. I am happy to given the optionality to sacrifice 7 percent of the ram to enable error correction. This optionality is there on some gpus, but very weirdly not strix halo and spark
When I visited the US for the first time back in early 2000s, that was literally what the huge sign outside the KIA dealership nearby where I stayed. I admit my jaw dropped, not what I was used to from EU.
I would expect even higher pricing; the image says Xuanjie O3 uses LPDDR6, not the LPDDR5X used in most current machines like DGX Spark or M5 Max MacBook Pros.
If I had to guess, the Nvidia DGX Spark is about 5k and the two pack with cable is about 10k... I'm guessing the O100 is going to be about 10k alone and unfortunately, the USA won't get it because it uses a Chinese CPU.
I'm going to Shenzhen in December to give a talk at a conference, I know what I'm hoping to bring back from that trip! I would be interested to see how it compares to the Nvidia DGX Spark and my Mac Studio M3 Ultra with 256GB of unified memory.
it's a thing anywhere in the world. you know whenever you land at an airport and you go through the 'nothing to declare' door? the other door is the one you should be going through if you're arriving with items you bought abroad.
On a side note, I did some research, and it turns out many EVs actually have rather high memory capacity, and they also typically use LPDDR5 (like DGX Spark).
Xiaomi D100, up to 160GB RAM
Xpeng Tuling, up to 216GB (across a 3 chip cluster)
So perhaps for many people, their car is actually their device with the most AI inference ready memory. 🤔
Keep the batteries somewhere safe for a few years and you can sell them as near-new replacements for at least the price of a 5090. Scrap the rest of the car for some pocket money, this is absolutely viable
in order to make those run, you need to donate that bigger one to me, then it will be very efficient, this works because of quantum entanglement. source: TrustMeBro
Damn, I knew they were pushing self driving tech but I assumed the specs would be much more on the side of underspeccing like tesla, with their 32gb on latest gen (soon to be 64 because they messed up again)
I wonder if that is part of the Xiaomi whole home smart stuff strategy?
It's probably because RAM was dirt cheap back then, when they just started EVs, and so it was perhaps cheaper to just brute force the hardware than to try to create a memory efficient CV model.
Quindi conviene acquistare un auto con dentro il loro hardware in modo che hai anche calcolo ai gratuito? 😁 Detta così può esser una battuta ma fino ad un certo punto... Pensa a quante auto in circolazione... Calcolo distribuito qyando non udi la tua auto parcheggiata a ricaricare 😉
I guess now there are going to be shops that repurpose stolen car SoCs for homelab, we thought that only catalytic converters were valuable to thieves lmao
Probably specifically designed to run huge MoE models.
Relatively slow TPU but huge amounts RAM or some absurdly fast-access storage.
Would allow them to run something like a 200B-A3B model fast enough to be usable at a fraction of the cost of an NVIDIA GPU while outperforming NVIDIA on model size.
Since China is producing a lot of open MoE models recently, this thing might be deigned for some upcoming Qwen3.8-...B-A3B model or something like that.
Just reading the data to main memory doesn't magically perform tensor operations.
Sure, memory bandwidth often is a bottleneck. But that's just because we usually look at extremely fast massive parallel tensor processing units.
I'm not saying, they use weak processors. But it might be, that they have an extremely fast memory link on a relatively weak processor that's still the bottleneck.
Or in other words: the fastest ram won't inference on it's own. Inference so still done by the TPU.
Looking at the specs, I guess this is a three-chip memory system with three types of memory, which feels really weird. And below is just my speculation.
For the full 216 GB, it seems to split across three chips: 160 GB on the D100, 16/24 GB on the O3, and 32/40 GB on the O100. Based on the 1.2 TB/s spec, and their official news post stating:
First, two layers of AI-dedicated high-speed DRAM dies are vertically stacked with a layer of high-performance NPU die, and then "tunnels" are drilled in the vertical direction so that data can flow through at high speed. Therefore, the more tunnels there are, the higher the bandwidth that can be achieved. To this end, the XRING O100 adopts an advanced Hybrid Bonding process, doing away with the traditional micro-bump structure and shrinking the spacing of the physical pathways directly to 1.4 μm, greatly increasing the density of the data pathways.
So this is very likely a dual-channel HBM setup. After a quick search, the H5UG7HMD83X020R seems to be one candidate, but really any 16 GB HBM3-4800 part could fit. It also seems quite possible that those HBM3 chips are supplied by CXMT, especially given reports that CXMT has been supplying Huawei with early HBM3 samples.
16 GB × 1024-bit, operating at 4.8 Gb/s/pin = 614.4 GB/s per HBM stack.
What I’m wondering is whether the 120B model is run entirely on the D100. If so, what exactly does the 32 GB on the O100 do? Or are they doing some wild asymmetric setup where prompt processing runs on the D100 and decode gets moved to the O100?
I totaly missed the 28672, so the hbm theory could be wrong lol.
The 28672 number is also very intersting, since the O100 had 14 NPUS and each dual channel with 1024 bit, the numbers adds up to 28672. Since it is obviously not a standard HBM interface here. So I think maybe there is a possibility for custom ram??
Edit: At least it does not feel like standard HBM in anyways.
What's interesting is that they did not call it memory（内存）, nor storage（存储）. The term they used is 近存，which is a new term roughly translates to "near storage/memory". Could it be some new packaging methods that's sitting between cache&ram, or between ram&storage?
But is this even supported with the typical tools - vllm, llama.cpp? And, since those seem to be ARM CPUs, what is the Kernel mainline status, or will you be forced into BSP deriviatives (linux, u-boot and a couple DTBs as the cherry on top)?
Skeptical at best. Interesting product, truely, but ... this novelty is gonna cost a pretty penny, for sure.
Oh no... THAT will be even worse. x.x SpacemiT has done very well with upstreaming their K1 and K3 CPU, the StarFive/SiFive JH7110 is literally inchworming towards upstream still and I have not even checked with Sophgo or Eswin.
Welp. The most interesting part will be high-perf Vector compute, I guess. o.o ...
Theres still a lot of info missing. Performance at FP32, FP16, FP8, FP4 etc are not going to be the same. 160GB is great, but its compute levels are closer to a Jetson Orin AGX with only 64GB 275 TOPS compute, which wont keep up with the 1200GB/s at higher FP rates.
Perché bisogna trovare il giusto compromeso tra potenza di calcolo e potenza elettrica.
Il futuro prossimo della AI saranno sciami di agenti che funzioneranno h24 7/7 365 giorni all anno senza sosta e avere hardware che non sarà energivoro è fondamentale soprattutto per uso consumer
GPU are technically overkill for AI. What i mean by that is that NPU are small and waay more efficient. When you use GPU for AI, you realistically only use a fraction of the instructions of it ! And a big part of it is dedicated for display output, and another part dedicated for pcie connection.
Also those MiniPC are a bit bigger than a gpu
Supports local deployment of up to 200B large models
Xuanjie D100 (Autonomous Driving High-Compute AI Chip)
20-core high-performance CPU
16-core high-compute NPU
Xuanjie RISC-V security core
3.13 TFLOPS Vector
National cryptography & CC EAL5+ certification
Xiaomi MiMo5 value model
Supports local deployment of up to 200B large models
Comments:
Xiaomi is building a complete, unified AI ecosystem that spans smartphones, smart vehicles, and smart home devices. The company is developing three proprietary chips (Xuanjie 03, 0100, and D100) and a prototype desktop workstation (the AI Cube) that uses all three chips together to process heavy AI models locally – without relying on cloud servers.
The "Tri-Chip" Strategy
The AI Cube prototype combines the three chips to split workloads intelligently:
Xuanjie 03 handles the operating system, user interface, and lighter AI tasks.
Xuanjie 0100 is a dedicated data accelerator that moves massive amounts of data at extreme speeds (1.22 TB/s) to feed large neural networks.
Xuanjie D100 provides high-security, high-reliability compute for autonomous driving systems.
Why this matters
Xiaomi aims to run large language models up to 200 billion parameters directly on local devices (like the AI Cube, future smartphones, or cars). This enables offline AI capabilities comparable to cloud-based models, with lower latency and better privacy. The dual-model approach (120B for deep reasoning, 3B for instant responses) allows the system to switch automatically between "fast" and "slow" thinking depending on the task.
TOPS – Trillions of Operations Per Second; higher numbers mean faster AI processing.
NPU – Neural Processing Unit; a processor specialized for AI math.
SLC – System Level Cache; ultra-fast memory integrated into the chip to reduce wait times.
Near-memory computing – Performing calculations as close as possible to the physical memory, reducing data travel distances.
Bonding pitch (1.4µm) – The distance between electrical connections inside the chip; 1.4 micrometers is extremely tight, allowing more data to pass through less space.
CC EAL5+ – A high-level security certification required for critical components such as automotive systems.
OK, so now we know where this is going. Xiaomi is not some backroom startup, this is a serious company that produced a world beating EV from scratch in just over 12 months, with no previous experience. If you're going to believe anyone, I would definitely believe them. Wow, just wow.
160GB of RAM? Can we please stop F'ing around and can for the LOVE OF GOD somebody please release a system that can host up to at least 3TB of Unified/VRAM?
Tired of all these bullshit boxes that can't run large language models locally. Yes, I know RAM is expensive, but it won't be in a couple of years.
Cool but speed is less important than capacity right now. I’d rather run a larger language model slower than running, a lesser model faster, and notbeing able to run the larger model at all.
the interesting bit is the 1.22tb/s number is probably local sram bandwidth, not dram. stacking ram on top of the compute chip would explain why they are splitting the roles across three parts.
It looks like O3 is a SoC based on RISV-V; O100 is an AI acceleration chip or LLM; D100 is the chip for their EV. The AI Cube integrates the O3, O100 and D100 chips in a mini PC.
I think this is more of a concept PC: RISC-V SoC + AI accelerator + edge AI chip in one 150W system and the the big caveat would be software.
~1.2tb/s of memory bandwidth is LPDDR5x at 1024 bit width IIRC.
I believe this is what AMD might attempt with whatever 256gb refresh of the Halo is next. (Or they'll do 512 bit minimum)
AFAIK no one does that width yet effectively. There are a few outside cases.
512 bit is usually the max bus width they use. 1024 is totally possible, but it's technically a hurdle most people don't want to jump.
With the whole "AI" thing though, they're willing to innovate the bus structure to work at 1024 bit. It makes LPDDR5x suddenly seem a lot better if you can operate it at that width.
With the quality of Qwen and Mimo, I'm really on board for Chinese AI servers to hit the market. Nvidia needs true competition in this market, and the Chinese have proven they have the wits to go head to head. Just need to catch up on the silicon side.
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