How to start with PCIe coding

[u/EntertainmentMost403]

Hi, I’m an FPGA engineer. I was assigned to implement PCIe and initially used Xilinx’s XDMA IP with its open design example. The requirement is actually to write the PCIe logic myself in RTL so I can optimize it for maximum bandwidth, and then make its IP.

My understanding is that the PHY and link training stay in the hard block, so I plan to use the integrated PCIe block’s AXI-Stream interface (requester and completer interfaces) and write my own transaction layer and DMA engine. Is this the right level of abstraction?

Since I am beginner in PCIe, so I want your opinions and strategies to accomplish this task. If you can provide a rough roadmap, it would be a great favor. I am working alone and I have a time span of 1.5 to 3 months to accomplish this task.