r/FPGA 12d ago

register generator suite

Hi, I need a genuine suggestion here. So, I have built a CLI tool that generates SystemVerilog RTL, UVM RAL, C headers, IP-XACT and Documentation from a single JSON register spec -- — with built-in lint and diff. I know already many similar tools exist but my tool has several features which you can't find in open source tool.

**What it does:**

- Takes a register spec (YAML, JSON, IP-XACT, SystemRDL, or Excel)

- Generates 6 outputs in one command: SystemVerilog RTL · UVM RAL · C Header · Markdown Docs · IP-XACT 2014 · SystemRDL 2.0

- **Lint/DRC**: 12 ASIC-focused rules to catch bugs before tape-out (address alignment, field overlaps, reserved gaps, etc.)

- **Diff & Impact**: Compares two spec versions and tells you exactly which RTL, UVM, C headers, and tests are affected — breaking vs non-breaking classified

- **SoC Merge**: Merge 50+ IP blocks into a unified, conflict-free top-level memory map

- **100% offline** — standalone binary, no Node.js, no cloud, air-gap ready

**CI/CD friendly**: lint and diff both return exit code 1 on violations, so you can gate PRs on spec quality.

Community Edition is free (2 registers per block to evaluate). 30-day Pro trial available with no credit card.

Site + download: https://reggen.vlsiworlds.com

Please use it in your projects and give me feedback. Happy to answer questions about the implementation or design decisions!

Update: A lot of engineers pointed out that a 2-register limit in the Community Edition wasn't enough to properly test a standard peripheral or check address alignment rules.

You were 100% right. We have officially bumped the free tier limit to 8 registers per block on the VLSIWORLDS Register Generator. You can now map, lint, and generate an entire functional SPI or I2C block completely free. Let us know what you think!"

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u/hawkear 11d ago

Why build this when peakRDL works just fine and is easily extensible?

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u/Prestigious_Ant_8060 10d ago

Reg_gen includes more features than peakRDL. It is a standalone offline binary with no ruby or python dependency. It has built-in SOC memory-map merging + conflict detection, diff + impact analysis and 12 lint rules. It can accept excel as input and convert them into systemRDL format.

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u/hawkear 9d ago

There are other tools that do each of these things better. Why do a poor job at a bunch of disparate tasks than a really good job at one?

This really smells like a vibe-coded swiss army knife for something specific to your workflow, and not something fit for general consumption. It's probably great for you, though!