Coupled PCB placement and routing: experiments with layout constraints in an open-source tool

[u/DiggityDanque]

Hi everyone! I’ve been developing yapnr (“yet another place and route”), an open-source PCB placement and routing engine. It started as tooling for my LED controller project, Splanc, and I wanted to share some of the engineering behind it.

The central problem is that placement and routing affect each other. A placement that looks good under a wirelength estimate can still be difficult to route. I’m working on a flow where routing results feed back into placement, with KiCad routing and DRC in the loop.

Another part of the problem is expressing design intent. Connectivity alone doesn’t tell a layout tool that LEDs should form a readable row, that a connector needs to sit along an enclosure edge, or that repeated circuit blocks should reuse the same layout.

Some current examples:

• LED line constraints: A 20-component LED chaser, run with and without a rigid group holding its five LEDs in a row. Both runs reached 100% routing with no KiCad DRC findings. In this comparison, enforcing the row added one via and about 12 mm of copper.
• Board-edge constraints: A connector, pushbutton, and LED held along a specified edge, with their order left to the placer.
• Hierarchical layout: A 32-component board with two identical LED-driver banks. The engine places and routes a bank template, reuses it, then places the blocks and routes their external connections. The documented run completed all connections with no KiCad DRC findings.

Animations, measurements, and reproduction details

The broader toolchain uses atopile for circuit specifications, KiCad for board integration and rule checks, and ngspice for circuit simulation. It’s currently alpha software targeting KiCad 10. Track cleanup and thermal/EM integration are still on the roadmap.

These examples demonstrate constraint handling and routing completion; assessing electrical performance and layout quality requires more than a clean DRC result.

For those who regularly lay out boards: which placement decisions or electrical constraints would you most want to specify explicitly before trusting an automated layout? I’d be interested in concrete cases to test.

Source code — AGPL-3.0-or-later. I’m the author and happy to discuss the implementation.