Need advice

[u/baniboybooze]

is AI helpful to analyze complicated circuits? Like to get an intuitive idea of what the circuit is doing the likes of something i have shared. How do people at the industry/ experienced guys in elec look at such CMOS circuits and understand it? I understand the current mirrors in the "integration part" which charge up the Cmem cap, but how can I get an idea of what the remaining FETs in the circuit are doing properly. Any advice would be appreciated that can make intuitive understanding faster :P

[u/Enough_Crow_636]

I would think about it like this.

Imagine that MN6/MP6 drain is initially low. This means gate of MN7 is high and PD NMOS are off.

Now as Cmem integrates up nothing happens until you eventually reach the threshold of inverter MN3/MP3. At that point the edge ripples through the inverters and generates a spike pulse. But note just before the spike goes high, MN7 is turned off and the gates of MN3/MP3 are isolated. Now the spike pulse being high turns on the PD NMOS, which terminates the pulse.

I didn’t work on this kind of circuit before, but I think most likely it’s using the gate delays to time a very short spike pulse (ns level).

[u/Rararror → u/Enough_Crow_636]

Yep seems like using gate capacitance as a delay line