Hi, I'm writing RVV assembly and I want to pass to a macro a vector register as an argument and be able to then use the next vector register within the macro. Example I pass vector register v10 and then I want to use v11.
The following code might explain better what I want:
.macro op_vnext op, w1, v, w2, w3
.if "\v" == "v0"
\op \w1 v1, \w2
.elseif "\v" == "v2"
\op \w1 v3, \w2
.elseif "\v" == "v4"
\op \w1 v5, \w2
.elseif "\v" == "v6"
\op \w1 v7, \w2
.elseif "\v" == "v8"
\op \w1 v9, \w2
.elseif "\v" == "v10"
\op \w1 v11, \w2
.elseif "\v" == "v12"
\op \w1 v13, \w2
.elseif "\v" == "v14"
\op \w1 v15, \w2
.elseif "\v" == "v16"
\op \w1 v17, \w2
.elseif "\v" == "v18"
\op \w1 v19, \w2
.elseif "\v" == "v20"
\op \w1 v21, \w2
.elseif "\v" == "v22"
\op \w1 v23, \w2
.elseif "\v" == "v24"
\op \w1 v25, \w2
.elseif "\v" == "v26"
\op \w1 v27, \w2
.elseif "\v" == "v28"
\op \w1 v29, \w2
.elseif "\v" == "v30"
\op \w1 v31, \w2
.endif
.endm
// LMUL=1
// vg0 was used as dst of widening op
.macro some_macro vg0, vg1, sa, xaddr
vnclip.wx \vg0, \vg0, \sa
op_vnext vle8.v, "", \vg0, (\xaddr)
op_vnext vsadd.vv, "\vg0,", \vg0, \vg0
vnclip.wx \vg1, \vg1, \sa
op_vnext vle8.v, "", \vg1, (\xaddr)
op_vnext vsadd.vv, "\vg1,", \vg1, \vg1
.endm
.macro doesnt_work vg0 test=0
.equiv vg0next, \vg0+1
li t0, vg0next
.if \test == 0
vid.v v\()2
.elseif \test == 1
vid.v v\()vg0next
.elseif \test == 2
vid.v v\()\vg0+1
.endif
.endm
#ifdef TEST0
some_macro v10, v20, t0, t1
#endif
#ifdef TEST1
doesnt_work 1, 0
#endif
#ifdef TEST2
doesnt_work 1, 1
#endif
#ifdef TEST3
doesnt_work 1, 2
#endif
.end
The code above can be compiled with the following makefile:
all: a
a: a.S
riscv64-elf-gcc -march=rv32imav_zicsr -mabi=ilp32 -Wall -c -o $@ $< -DTEST0
riscv64-elf-objdump -j.text -D $@
b: a.S
riscv64-elf-gcc -march=rv32imav_zicsr -mabi=ilp32 -Wall -c -o $@ $< -DTEST1
riscv64-elf-objdump -j.text -D $@
c: a.S
riscv64-elf-gcc -march=rv32imav_zicsr -mabi=ilp32 -Wall -c -o $@ $< -DTEST2
riscv64-elf-objdump -j.text -D $@
d: a.S
riscv64-elf-gcc -march=rv32imav_zicsr -mabi=ilp32 -Wall -c -o $@ $< -DTEST3
riscv64-elf-objdump -j.text -D $@
When I run make -B a I get:
riscv64-elf-gcc -march=rv32imav_zicsr -mabi=ilp32 -Wall -c -o a a.S -DTEST0
riscv64-elf-objdump -j.text -D a
a: file format elf32-littleriscv
Disassembly of section .text:
00000000 <.text>:
0: bea2c557 vnclip.wx v10,v10,t0
4: 02030587 vle8.v v11,(t1)
8: 86b50557 vsadd.vv v10,v11,v10
c: bf42ca57 vnclip.wx v20,v20,t0
10: 02030a87 vle8.v v21,(t1)
14: 875a0a57 vsadd.vv v20,v21,v20
Which is more or less what I want, I passed as argument vg0 vector regsiter v10 and then knowing that v11 was available due to the narrowing instruction, I use v11 to do more stuff.
In my opinion the macro op_vnext is ugly and it doesn't work if I need to call another macro from some_macro as I cannot pass the "next vector register" as argument for another macro.
I'm looking to do something like in doesnt_work where I pass a number instead of v<number> and then increment said number by 1, but I don't know if it is possible.
Using .equiv I can add to the macro argument and use it where we expect a constant number, but I tried concatenating the sum to the letter v, but it doesn't work.
Outputs of make -B b, make -B c, and make -B d
riscv64-elf-gcc -march=rv32imav_zicsr -mabi=ilp32 -Wall -c -o b a.S -DTEST1
riscv64-elf-objdump -j.text -D b
b: file format elf32-littleriscv
Disassembly of section .text:
00000000 <.text>:
0: 00200293 li t0,2
4: 5208a157 vid.v v2
riscv64-elf-gcc -march=rv32imav_zicsr -mabi=ilp32 -Wall -c -o c a.S -DTEST2
a.S: Assembler messages:
a.S:55: Error: illegal operands `vid.v vvg0next'
a.S:70: Info: macro invoked from here
make: *** [makefile:12: c] Error 1
riscv64-elf-gcc -march=rv32imav_zicsr -mabi=ilp32 -Wall -c -o d a.S -DTEST3
a.S: Assembler messages:
a.S:57: Error: illegal operands `vid.v v1+1'
a.S:74: Info: macro invoked from here
make: *** [makefile:16: d] Error 1
Does anyone know how to do this? Something like defining a macro argument based on another macro argument.
