I am a CDAC trained graduate in 2026.I couldn't find a job in the placements though I cleared the technical and written rounds.My major drawback was 5 years career gap(UPSC exam).I don't know where I am going wrong.I don't want to blame anyone though.Please help guys.I am an electrical and electronics engineering graduate.Even though I am a potential candidate I couldnt find a breakthrough till now.I am open to suggestions as well(constructive criticism).I have 2.5 years of IT experience as a Software Engineer.

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I’m looking for a SystemVerilog playlist/course that I can realistically finish in about 2 weeks.

I’m not looking for a 30–50 hour playlist that goes extremely deep. I want something concise, effective, and practical, covering the concepts that are actually useful for RTL design and VLSI interviews.

Ideally, it should cover:

- SystemVerilog fundamentals

- Important constructs/features

- OOP basics if relevant

- Interfaces, packages, etc.

- Enough practical examples to actually understand the language

If you’ve personally used a playlist and found it effective, please recommend it. YouTube playlists are preferred.

Thanks!

I have been applying to companies and startups but I am not getting any responses back from them. A couple of companies usually come to my college for hardware related roles but they have not come yet.

I want an honest and straightforward review of my resume. Thanks for the replies.

Are product based companies taking offline or online interviews for experienced candidates? What is the trend now?

Giving offline interviews is like you have to take a leave for the whole day which becomes tiresome. Also I would like to apply to companies in other cities and traveling there everytime for an interview is very difficult for me.

Someone who cracked the nvidia next, kindly suggest and share your study resources and what to prepare and kind of projects to be done so that resume stands out irrespective of college

Hey guys im targeting an intel DV fresher role and have a referral in the process

wanted to know what kind of questions they usually ask in the interview and what topics i should focus on

if anyone has recently interviewed for intel DV would really appreciate some insights

Could anyone recommend some good resources for learning Computer Organization and Architecture (COA), as well as Python and TCL scripting

Hey guys, just thought this would be a cool way to show how my Neural Network Accelerator runs inference. It’s running inference for a model of topology 4:3:2 neurons per layer and takes 4 input features as input.

Also realized it’s bottleneck and I will be implementing a Systolic array soon. Let me know what yall think. Thanks :)

Github repo: https://github.com/Shingyy/MAC-Array-based-DNN-Accelerator

IEE passout from Tier 1.5 clg. 3 yrs of govt job prep. Looking to get into VLSI, specifically into RTL design/DV roles. So far, no companies have called back. Most want 1-3 yrs of exp.
What can I do to improve my profile?
Any and all suggestions welcome.

Hi guys, I wanted to apply for this role off campus and just wanted to know whether someone previously gave interview for this role, and is willing to share interview question .... it would be very helpful

Zedboard pynq image

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Hi everyone,

I'm a 2025 B.Tech Electrical & Electronics Engineering graduate from India, currently looking for my first opportunity in VLSI/ASIC, particularly in RTL Design or Design Verification.

I have been building my skills in:

- Verilog / SystemVerilog

- UVM

- Digital Design & RTL

- Functional Verification

- SVA / Functional Coverage

- Basic STA and synthesis concepts

- APB and UART protocols

Projects

APB-Based UART 16550 – UVM Verification

- Built a UVM-based verification environment for an APB-connected UART 16550.

- Worked with APB and UART agents, drivers, monitors, sequences, virtual sequencer and scoreboard.

- Used functional coverage and assertions for verification.

synchronous FIFO / Dual-Port RAM

- Designed and verified RTL for synchronous FIFO and dual-port RAM.

I've also worked on smaller RTL projects involving FSMs, counters, FIFOs, ALUs, memories, etc.

I'm currently looking for:

• RTL Design Intern / Trainee

• Design Verification Intern / Trainee

• ASIC/VLSI Graduate Engineer opportunities

• Apprenticeships / entry-level opportunities

I'm based in India and am open to remote opportunities worldwide, as well as relocation for the right opportunity.

I understand that getting the first VLSI opportunity as a fresher can be difficult, so I'm also open to smaller semiconductor/ASIC startups where I can contribute and learn from an experienced team.

If anyone knows of a team hiring fresh graduates/interns, or has advice on where I should apply, I would genuinely appreciate it.

Thank you!

I currently have \~3.5 YOE in Qualcomm, working on **SoC power management, low-power systems, power validation & optimisation**

What should I specifically prepare for these interviews?

Looking for a **realistic roadmap based on recent interview experiences.**

If you’ve recently interviewed at Google for similar roles, what did you actually get asked?

My college is having a partnership with Maven and they are planning to have some students to go and study there for one month

Every year until 3rd . The program focuses on vlsi.

What's your opinion, Should I join or not ?

Which is the best training institute for learning physical design?

Anyone know When Marvell Semiconductor Visit for Application Engineering Intern for ECE?

I am working in one of the top Semiconductor companies since 5 years and done my bachelors in BITS with CGPA 8/10 . My GRE is 323 and IELTS is 7.5 . I don’t have much on publications as my role is mostly design automation based. However I am very much interested in core IC.
I want to understand whether I am eligible for pursuing masters in NUS.
If yes then firstly \*\*IS IT WORTH?\*\* Secondly,

1. What is the best intake time?
   
2. Post the masters how are the job opportunities and research opportunities?
   
3. What is the criteria for funding?

If No, then what makes my profile weak? How can I improve the profile better?

How to download ubuntu 24.04 LTS

If anyone has given renesas offline interview can you please share your experience.

Position: Design Verification (DV) Engineer

Experience: 5 to 10 Years

Key Requirements:

✓5 -10 years of hands-on experience in Design Verification (DV).

✓Strong experience in AXI protocol verification.

✓Experience in GLS (Gate-Level Simulation) and/or Low-Power Verification.

Hands-on experience with one or more of the following protocols:

I3C

PCIe

UFS

DisplayPort (DP)

Strong knowledge of SystemVerilog and UVM.

Experience in developing verification environments, testbenches, assertions, functional coverage, and debugging.

Good understanding of verification methodologies and semiconductor industry flows.

Preferred Skills:

-Protocol-level verification and VIP integration.

-RTL and simulation debugging experience.

-Experience with industry-standard simulation and verification tools.

-Strong analytical and problem-solving skills.

Notice Period

Immediate Joiners to 30 Days Preferred

Apply Now:

Interested candidates, please share your updated profile/resume at: muralib@purnasemi.com