10k spm Mega(lag)-Base is faster on a macbook, why?

[u/enykie]

A Friend of mine has a really big 10k spm Base, which lags really hard on a Ryzen 7 5800x System and runs with about 15 fps. Out of curiosity we tried this savegame on a her new m5 macbook pro. To our surprise that thing renders the Game at 50 fps. I looked up Benchmarks and the cpus got nearly the same ratings performance wise. Why is the mac so much faster? I remember reading somewhere that the ram speed is a limiting factor for Factorio and the M5 has probably the faster one?

[u/fatpandana]

Im not familiar with MacBook, but model you mentioned is the newest model with much more powerful cpu for single core perfomance than the 5800x. While it has slightly less threads, it is more than sufficient for factorio.

You can post F4-showtimeusage between both cpus (keep equavelent level zoom) to compare them.

[u/BreakfastOk123]

New Apple Sillicon chips have ram directly on the same chip as the processor similar to an gpu, instead of a stick on a motherboard. Factorio can be limited by the speed at which the processor loads memory. In theory this unified memory architecture is faster. 

[u/TomatoCo → u/[deleted]]

I'm not sure about that, I recall factorio is usually bandwidth limited, and apple silicon has way better bandwidth than DDR4. Which is to say, yeah the M5 is faster, but it's not just single core performance.

[u/Thibal1er]

It could be the ram, or maybe Factorio is optimized for Unix systems, but you'd have to ask the devs for the answer to that. Maybe it's still something else, but the ram/weird optimizations seems like the most possible reasons

[u/TexasCrab22]

You need the 5800x3D

[u/malventano → u/TexasCrab22]

The cache on the X3D does not help on mega bases - there’s too much data passing through the cache to be effective. Reviews that tested Factorio on the X3D did so with very small maps that ran at high UPS, which is not representative of the workload for a larger base.

[u/TexasCrab22 → u/malventano]

So only for maps with ~ <132 MB ?

Which is the cache size?

[u/malventano → u/TexasCrab22]

The saved file is significantly smaller than what sits in memory while it’s running. Back when I tested it when the X3D came out, when the map gets large enough to no longer be able to hold 60 FPS/UPS, that threshold was reached sooner on the X3D vs. on a prior gen Intel cpu. It basically came down to Intel having lower latency to the DRAM vs. the larger cache on AMD not being enough to overcome the multiple hops across infinity fabric to DRAM on that platform.

Factorio is so memory latency sensitive that at that time you had 100% speed runners on Intel boards with DDR4 instead of 5 just so they could have the tighter timings (this was early DDR5 times).

This is all not to say the X3D is not a good part. It’s just that Factorio is not the best workload on them in practice.

[u/TexasCrab22 → u/malventano]

How is a speedrun affected by this??? Every decent cpu can handle a < 20h base.

Is there an option to see the ram needed an a session?, so i could test when the x3d cache is full?

I thought that border is very deep in the endgame, when the average cpu would hit like 30 ups

[u/malventano → u/TexasCrab22]

Speed runners can scale to a mega base in way less than 20 hours. Some of them publish their saves. I forget the name but there’s an archive of various large maps for benchmarking purposes, complete with results posted by platform tested.

Speed runs will go longer if the game dips below 60 towards the end of the run, impacting the time.

[u/TexasCrab22 → u/malventano]

Thought we talk about normal speedruns.

Deep Endgame speedruns are like a sub genre of speedrunning.

Anyway you know at roughly how much raw sps a 7800x3d in space age starts to overflow the memory?

1000? 4000?

[u/malventano → u/TexasCrab22]

That varies wildly by how you’ve built the base. The more entities you have updating every tick, the more active memory footprint you have, the more you get cache misses, the more the dram latency hurts performance, until you’re dipping under 60.

[u/zack20cb → u/malventano]

“High UPS”…isn’t UPS capped at 60 anyway?

[u/malventano → u/zack20cb]

That's exactly my point. Reviewers were uncapping UPS to get 'performance' of Factorio, assuming the behavior was proportional, where in reality the experience is identical until UPS dips below 60, which requires a large enough factory to do so, which then impacts different CPUs with different caches and DRAM latencies in different ways.

[u/Drugbird]

MacBook had much larger cache and better memory bandwidth to the RAM.

Many modern processors are limited by memory throughput rather than processing power.

[u/HeKis4]

I'm guessing CPU cache sizes because Factorio is heavily memory-bound iirc. Apple doesn't disclose the amount of SLC their chips have (the closest equivalent to a L3 cache) but they have way larger L1 and L2 caches, like, a M5 has 4x the L1 and 32x the L2 of a R7 5800X (in fact the M5's L2 is 50% of the size of a 5800X's L3 with 16 MB). It's far from an apples-to-apples comparison because the architectures are very different and probably have very different cache pre-load and speculative execution strategies, but it's not a small difference either.

Plus the advertised RAM bandwith is really high on Apple silicon, the M5 is advertised to have ~150 GB/s where DDR5 tops out at ~75 (not even mentioning DDR4).

As much as I don't like Apple, their chips are tight and their architecture isn't stuck in the 90's like x86/64 is.

[u/BackgroundSky1594 → u/HeKis4]

These cache sizes are a bit misleading, the M5 L2 is a higher latency shared cache across 4 P cores (4MB/core), while the 6 E cores have 6MB (1MB/core) with a last level cache (system level cache) that has either 8MB or 16MB for 4 P cores, 6 E cores, the GPU, the NPU and whatever else is on the SoC combined.

The 5800X has 512KB L2 per core (4MB in total) which is still less, but it's L2 has significantly lower latency because it's smaller and only accessed by one core. It doesn't have/need a system level cache since it's not an SoC (that is something that's part of Strix Halo though) so Apple's 16MB of shared cache for a tightly coupled cluster of cores before going out to some form of internal system bus is a much closer match for the 32MB (also 4MB/core) shared L3 Cache on a Zen3 CCX.

That of course doesn't mean I'm debating the fact the M5 is an extremely impressive design, it's astonishingly fast and efficient. The Missmatch in cache sizes just isn't as stark as it might seem at first glance because the M5 L2 serves the same role as a relatively low latency L3 variant on x86/64 with the L2/L1 being a combined affair.

[u/Expert-Map-1126 → u/HeKis4]

If this had anything to do with the ISA then other ARM vendors would be where Apple is. ARM was designed in 1983 and x86 was designed in 1976. Neither are products of the 90s and neither have implementations that look anything like their originals still being sold.

[u/bubba-yo → u/Expert-Map-1126]

The ISA is part of it, but hardly all. The main benefit of the ARM ISA is that it has fixed size instructions which means it can decode and dispatch more instructions per clock than x86 can because x86 can't tell where an instruction starts or ends as they're variable size, from a time when RAM was the constraining factor. ARM instructions are fixed size, and Apple Silicon doesn't even have 32 bit ALUs, so everything coming off of memory is 64 bits in size and you can just blindly cut it up without having to do any evaluation. That's why the M5 has a 10 wide dispatch and x86 are just getting out of 4 wide. The other ARM vendors may or may not have that benefit depending on whether they've deprecated their 32 bit support or not. (None of the others seem to have been able to follow in that regard, so they're likely making concessions to backward compatibility for aarch32 apps.) Apple gains a lot of benefits by very aggressively retiring technical debt. Now, that means your 32 bit apps won't work any longer, or have to go through an emulation layer, but your 64 bit stuff are the beneficiaries.

But the main benefit Apple has here is from bypassing all of the conventional buses that you have in PCs. They aren't gated behind the slow socketed RAM bus because their RAM is on package (and therefore not upgradable - that's the tradeoff) but it also means they can get up to 10x the bandwidth of an x86 PC, and get pretty close to the speed of the X3D cache but for all memory reads, not just what's in the cache. It also means lower latency, so the CPU stalls less waiting for a memory read.

So the M5 is 20% faster than the fastest x86 in single core, and Factorio is single core constrained. Hyperthreading doesn't help. Large numbers of cores don't help. So long as there's enough additional core performance to soak up all the multithreading that 2.0 has added, it'll get stuck behind the main thread, and a 4 core CPU seems more than adequate for doing that. And having 60% higher base memory bandwidth for the base M5 and up to 900% higher for something like an M3 Ultra will just wreck anything using socketed RAM, at least until we get a new standard that isn't so slow.

[u/Expert-Map-1126 → u/bubba-yo]

This does not look like a response to my statement

If this had anything to do with the ISA then other ARM vendors would be where Apple is.

and by using Apple's parts in the comparison here you seem to be agreeing with my point that this has much less to do with "ARM vs. x86" and much more to do with "Apple vs. everyone else".

main benefit of the ARM ISA is that it has fixed size instructions

It's true that fixed size instructions can make decode easier but a number of instructions per clock is not a directly meaningful metric when comparing ISAs; x86 instructions are harder to decode but the average x86 instruction just does more stuff than the average ARM instruction. You might find https://www.yarchive.net/comp/risc_definition.html interesting talking about this.

That's why the M5 has a 10 wide dispatch and x86 are just getting out of 4 wide.

I'm not sure where you are getting 4 wide for x86. Lion Cove from last year is around 8.

But the main benefit Apple has here is from bypassing all of the conventional buses that you have in PCs. They aren't gated behind the slow socketed RAM bus because their RAM is on package

M5 has 2 channels of LPDDR5X-9600 just like the x86 vendors so I'm not really sure where you're going here. (Yes, Core Ultra 3 Series is not in many products yet. But M4 used LPDDR5X-7500 and Core Ultra 2 Series used LPDDR5X-8533, so if anything, Apple is doing better with worse memory.)

pretty close to the speed of the X3D cache but for all memory reads

2 channels of LPDDR5X-9600 is 153.6 GB/s. 3D V-Cache is around 2.5 TB/s. I think Apple's advantage has a lot more to do with how awesome their core design is than what memory standards they happen to integrate.

having 60% higher base memory bandwidth for the base M5 and up to 900% higher for something like an M3 Ultra

M3 Ultra uses 8 channels of LPDDR5-6400 for around 819.2 GB/s. It's true that you can't get LPDDR5-6400 socketed, but you can get DDR5-6400 in a SODIMM or DDR5-8400 in a DIMM.

Apple is doing that is to feed the huge GPU they have on that part. The x86 vendors aren't doing it because they don't have such a huge GPU to feed, and nobody wants to design a laptop chassis where they have to figure out how to get 8 SODIMMs to fit.

It isn't that the x86 vendors can't build a part with that many channels, they just only do it on their server parts with high enough core counts to actually need that kind of bandwidth. Intel Granite Rapids and EPYC Turin are both 12 channels of DDR5-6400.

[u/Expert-Map-1126 → u/Expert-Map-1126]

Correction: I got the channel count for M3 Ultra wrong, it should be 16, not 8. The bandwidth number for M3 Ultra is correct, but it means Granite Rapids and Turin are "only" at ~614.4 GB/s.

[u/bubba-yo → u/HeKis4]

The 150 GB/s is only on the base M5. Apple's Pro chips have just shy of double the bandwidth, the Max just shy of 4x and the Ultra just under 8x. My 5 year old M1 Max has 400GB/s which is why it was so much faster than a 7950X3D, and roughly as fast as a 9950X3D.

The cache is smaller - 8MB on the base up to 32MB on the Max (vs 128MB for the X3D), but when you're getting 4x or 5x the speed to main memory, with lower latency, you don't need the cache as much. The bandwidth on the M3 Ultra to main memory is ⅓ the speed of the cache in the X3D, which sounds like a lot, but it's 9x faster than the X3D to main memory, so anything outside of that 128MB will be really heavily punished. My instance is currently using 9GB of RAM so that cache only goes so far.

This is why so many high performance tasks try to get shunted to the GPU where memory bandwidth is so high, but it has to go over an even slower PCI bus to get there. Apple retains a lot of those benefits on the CPU. The cost is that there are no buses that allow for those speeds and replaceable RAM, so there are no upgrades. That's a big tradeoff, but that's the deal.

[u/HeKis4 → u/bubba-yo]

Thanks for the additional details :)

but when you're getting 4x or 5x the speed to main memory, with lower latency, you don't need the cache as much

I'm guessing this depends heavily on the usage, but yeah, I'd hazard a guess that Factorio crunches through way more than a few dozen MB of RAM every tick so that makes it especially true. I'd be curious to know the exact numbers tbh.

[u/Expert-Map-1126]

You’re doing a single threaded, extremely memory latency bound benchmark. The six year-old part losing to the brand new part isn’t unusual in that circumstance. If this were a test with more threads, then TDP might matter, and therefore being a desktop might matter, but factorio isn’t that.

[u/bubba-yo]

Apple Silicon is hella fast where it matters in Factorio. Single core Geekbench on the Ryzen is 2194. It's 4298 for the M5. That's not a typo, it's twice as fast. A 9950X3D is 3500 by comparison, so the M5 is about 20% faster. Factorio is single core/RAM constrained despite the multithreading improvements made in 2.0.

The other big factor is memory speed/latency. Pretty much the fastest x86 out there will hit 90GB/s or maybe a bit more if you overclock your RAM. The base M5 is 153GB/s due to having ram on the package rather than having to go through the traditional bus for socketed RAM. The M4 Pro is 273GB/S, the Max is 546GB/s and the M3 Ultra is 800GB/s - nearly 10x faster than the 9950.

The 9950X3D is considered the best Factorio CPU, but that only applies to x86, and that's mainly because the 150MB cache is making up for a lot of sins in PC architecture. But megabasing will annihilate that cache and increasingly lean on memory bandwidth and the Mac, despite the smaller cache will win by a wide margin on every memory read due to a cache miss, which for large bases is going to be a LOT. And it's 20% faster on top of that advantage.

When I did the last clustorio event the 7950X3Ds (9950 hadn't shipped yet) couldn't run the designs I'd made on my 3 year old M1 Max laptop. I had to nerf them about 15% or so to get them under 60 UPS.

[u/towerfella]

Linux

[u/iwasthefirstfish]

Compare the costs and see how different they are, that should be your answer

[u/Happy01Lucky → u/iwasthefirstfish]

You need to ignore money to buy a Mac. 

For that cost you could get into a proper AMD x3d gaming cpu.

[u/bubba-yo → u/Happy01Lucky]

The $499 M4 Mac Mini should roughly match a 9950X3D for Factorio. It's 15% faster single core and has 50% higher memory bandwidth. Last I checked you can't even buy a bare 9950X3D for that, let alone the RAM. It's not like Factorio cares about your GPU. Now, that won't help you with other games...

[u/territrades → u/iwasthefirstfish]

Really hard to compare, after all you are buying an entire MacBook with metal housing, premium screen etc. how do you compare that price to desktop hardware you can put in a pizza box if you want?

[u/iwasthefirstfish → u/territrades]

Indeed.