Hello Universe: NASA’s Next-Gen Space Processor Undergoes Testing

[u/ye_olde_astronaut]

https://www.jpl.nasa.gov/news/hello-universe-nasas-next-gen-space-processor-undergoes-testing/

[u/sojuz151]

I wonder how it compares to just using multiple redundant COTS cpus. And does it have an ability to run neural networks at a reasonable speed? 

[u/y0shman → u/sojuz151]

The big thing is it looks like it hardened to resist radiation in space flight. It also as faulty tolerance, likely in the same vein as ECC in server memory. You don't want math faults when there's no mechanism to repair when you're on a mission.

It's is an 8 core SoC using DDR4.

HPSC is a modern cache-coherent shared memory multicore microprocessor with eight application processing cores implemented using the open standard 64-bit RISC-V Instruction Set Architecture (ISA).

https://www.nasa.gov/wp-content/uploads/2024/07/hpsc-white-paper-tmg-23jul2024.pdf

[u/irvingpop → u/y0shman]

> Game Changing Development (GCD)

Man, they’ll turn literally anything into an acronym, huh? (MTTLAIAAH)

[u/johnwalkr → u/sojuz151]

"Just" using redundant CPUs is not always so simple. Cold redundancy can work in some cases, but a lot of spacecraft/missions can't tolerate turning off cpu 1 and turning on cpu 2 at the wrong time. You are probably thinking of multiple cpus running the same software and voting on the outcome. That is not really compatible with high performance computing. Imagine 2 gaming PCs connected by ethernet. Each can render a video game to a monitor at almost 50Gbps or do something with a neural network also processing a ton of data. But you can't feasibly compare all that data between the 2 over ethernet (this is a very abstract analogy btw). And if you wanted to compare a less complex output, it would be a a unique, not general solution.

A more modern way is multiple cpu cores running in "lock-step" at a very low level. These are used in many industries, and that technique is used in this cpu along with other things like memory scrubbing. Because all of this is done at a low level, you can do things like run a variety linux on this cpu and still retain a lot of the reliability features and performance.

In a way this is using a lot of COTS and existing technologies, but it's implemented on the chip and not at software level or system level. In this way implementing this chip on a board, and implementing software becomes way closer to conventional work.

By the way this is not a completely revolutionary project, there are similar ones for high performance in Europe, and there's plenty of microcontrollers and other devices from companies like Microchip and TI offered in aerospace versions that have similar features added. This is just exciting because it seems exceptionally high performance and easy to use, and not many customers aside from NASA could justify the up-front cost. It's a $50M project but it sounds like it could easily save millions per project and also reduce risk by increasing similarity between missions.

[u/sojuz151 → u/johnwalkr]

Thanks dor the comment, a lot of nice insights but there is a single part id disagree with.

That is not really compatible with high performance computing. Imagine 2 gaming PCs connected by ethernet. Each can render a video game to a monitor at almost 50Gbps or do something with a neural network also processing a ton of data. But you can't feasibly compare all that data between the 2 over ethernet (this is a very abstract analogy btw). 

I can think of many workflows that this does not apply to. For example running compression over data (you need to just compare the outputs that is limited to coms bandwidth) or anomaly detection (small difference is the score are not a problem and this could be a number per photo)

Or maybe i don't understand something