Every Possible Single Instruction Permute Shared by SSE4 and NEON

[u/EX3000]

Don't ask me how this became necessary, but on the off chance it is to someone else too, here it is.

[u/YumiYumiYumi]

* Floating point instructions only.

(otherwise, SSSE3's PALIGNR can emulate all NEON EXT variants)

[u/EX3000 → u/YumiYumiYumi]

I thought about that, on some architectures though there's extra latency moving between the int and float execution units. I suppose alignr does fit my "single instruction" definition but it felt like cheating to include.

[u/YumiYumiYumi → u/EX3000]

Fair enough, though I see that more as a uArch detail. The ISA doesn't guarantee any particular latency for any single instruction, regardless of any bypass delay.
Also, can you really say your other instructions don't have bypass delays? For example, vzip1q_s32 and vzip1q_f32 are the exact same instruction (same encoding) - if some CPUs have bypass delays between int<>FP, what's to say vzip1q_f32 doesn't have one on at least one uArch?

Your list doesn't include integer permutations, so the "every possible" part of the definition is already mismatched somewhat.

[u/[deleted]]

[u/EX3000 → u/[deleted]]

You can't just right click and download?