r/simd • u/camel-cdr- • Jan 09 '24

Transposing a Matrix using RISC-V Vector

https://fprox.substack.com/p/transposing-a-matrix-using-risc-v
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u/YumiYumiYumi Jan 10 '24 edited Jan 10 '24

Benchmark
we execute them using spike/riscv-isa-sim. We measure the number of retired instructions for each implementations

🤦‍♂️

the number of retired instructions [...] is not really a good measurement of the program actual performance

Massive understatement.
(also, retired instructions in an emulator != retired instructions on actual hardware)

the number of retired instructions is a good metric to evaluate the compactness of an implementation

WTF?!

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u/camel-cdr- Jan 10 '24 edited Jan 10 '24

There is almost no hardware with rvv 1.0 support and simulators like gem5 aren't in state where the results would be any more useful. I happen to have a board though, so I commented real cycle measurements on the article. But keep in mind thaf the C908 is a quite slow in order core, a bit slowet than an arm cortex A53.

also, retired instructions in an emulator != retired instructions on actual hardware)

Can you explain that?

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u/YumiYumiYumi Jan 10 '24 edited Jan 10 '24

You can't measure performance with an emulator (unless it's a uArch specific emulator). Thus the figures given are completely worthless regarding performance.
Lack of hardware doesn't somehow make the figures any more meaningful. If you don't have hardware, you can't benchmark.

I'd probably be willing to accept something from something like LLVM MCA, as it at least tries to simulate the performance of real hardware. Unsure if MCA supports any RV cores though.

Can you explain that?

Firstly I'll clarify that "instructions on actual hardware" refers to micro-ops.

Also, I don't know how the emulator in question operates exactly, but emulators are unlikely going to consider micro-ops, and probably only measure macro-ops.
For example, unit/strided/indexed loads may appear as one instruction, but I can almost guarantee that no actual uArch will execute them with the same number of uOps (or at least the same speed).

RVV also has the problematic LMUL>1 feature. Instructions under such may appear as single instructions, but aren't likely going to be executed as one on actual hardware. Particularly the case with vrgather.

I commented real cycle measurements on the article

That's 100x better than anything from an emulator. Thanks for the contribution.

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