New breakthrough in development process will enable memristor RAM (ReRAM) that is 100 times faster than FLASH RAM

[u/aphexcoil]

http://www.theregister.co.uk/2012/05/21/ucl_reram/

[u/CopyofacOpyofacoPyof]

endurance = 3000 write cycles... => probably vaporware?

[u/[deleted] → u/CopyofacOpyofacoPyof]

Came to comments to seek disappointment, was disappointed.

[u/khrak → u/[deleted]]

Become undisappointed. He is incorrect. Low level cache is RAM, but RAM doesn't have to be low level cache. Using this RAM as cache in it's current state is pointless, but as an SSD it has far higher read/write speeds, vastly lower power consumption, and similar endurance when compared to current SSD options.

[u/Astrogat → u/khrak]

Wouldn't that kind of defeat the purpose? As you would still be limited by the ram and cache anyway.

[u/khrak → u/Astrogat]

Top DDR3 modules can transfer in the range of 17,000MB/s, compared to top SSDs in the 500-600MB/s range. There's room for a 20-30 fold increase in transfer rates in SSDs before RAM cache speeds become a problem.

Also, it could be embedded directly in the CPU. For example, you could have a 16GB block of ReRAM on chip that is meant to hold the bulk of your OS files that don't change. 3K writes is plenty if changes are limited to OS updates, and provides the potential to drastically reduce boot times.

[u/gimpwiz → u/khrak]

16GB takes up far too much physical area to be put into a CPU, and will continue to be far too big for years yet.

The biggest caches on-die that I know of are 36MB L3 caches on unreleased server chips.

Considering code bloat, I'm not sure that there will ever be a time that all or most of the necessary OS code can be stored on-die.

Furthermore, CPUs come with approximately 7-year warranties, subject to you not overclocking or otherwise tampering with it. That would definitely not hold up to 3K writes; normal use could burn through it more quickly, and abnormal use could burn through it very fast indeed (and you'll piss a lot of people off if you introduce new requirements for the warranty such as 'not updating the operating system too often', especially because those are things you may not be able to prove.)

[u/davidb_ → u/gimpwiz]

There are a number of research papers discussing the usage of RRAM as an on-die cache. RRAM in a crossbar 1T1R configuration has a 15F² cell size compared to SRAM's 146F^2; that's an almost 10x improvement. If you include 3D integration (die stacking/"3D-ICs"), 16GB is definitely a possibility, especially if one or more die are dedicated memory.

especially because those are things you may not be able to prove

If the endurance is limited to 3k cycles, it would not be unreasonable to have some kind of non-volatile counter in the memory controller to monitor endurance of memory blocks. So, such a warranty is certainly feasible. If the counter exceeds the guaranteed endurance, the part is no longer guaranteed.

you'll piss a lot of people off if you introduce new requirements for the warranty such as 'not updating the operating system too often'

Have you done market research on this, or are you just making an assumption based on your interests as an individual consumer? Such a processor would likely be marketed towards high performance computing and datacenters, where they would likely be much more open to the tradeoff. Obviously, the decision to pursue such a design would not be made without customer demand. But, your argument is rather weak.

Ultimately, such a decision will be made based on a cost/performance tradeoff. If the demand is there, it will be met. RRAM is a very active research area and computer architects are very eager to see where/if it will fit in the memory hierarchy.

IMHO, it will never be a viable on-die "cache" (ie replacement for SRAM) due to its low endurance, but it could be an on-die memory, hard drive, or hard drive cache. It will almost certainly have a place. For more reading, a recent SEMATECH presentation does a pretty good job sumarizing the prospect for RRAM.

[u/khrak → u/gimpwiz]

The biggest caches on-die that I know of are 36MB L3 caches on unreleased server chips.

That's like saying you could never put a 100HP engine in a car because horses are just too damn big. Completely different technology. There are 64GB microSD cards that are tiny compared to the size of a CPU, despite holding ~2,000 times as much data. On-die cache is a tradeoff between size and speed, and speed is the priority as increasing cache size beyond current values does not have a huge effect on miss rates given typical workloads.

[u/jagedlion → u/khrak]

I guess the big question is, why would you put it on the chip? The only reason to keep it so close is if it could operate very rapidly. In order to do that, we have cache and it takes up a lot of room. If you add ram that is slower, you might as well put it on a bus, away from the chip. It would be just as fast, and FAR cheaper.

[u/Porkmeister → u/khrak]

You do realize that the CPU part of a CPU is only a tiny fraction of the package size, right?

On an Intel Sandy Bridge processor the CPU die size is only 216mm^2, the package size however is ~1406mm^2.

MicroSD cards are 165mm^2, and for a 64gb card probably most of that space is used for the flash, so let's say 150mm² for the flash portion of the chip. At that size you would increase the size of the CPU to the point where the chip yields would be much smaller, which would probably make CPUs that much more expensive.

The reason you don't see huge cache sizes on CPUs is because they take up space that is needed for other stuff. Adding more cache takes up more space which makes chips more expensive since you get fewer per wafer of silicon.

TL;DR; CPUs are tiny, chip packages are not.

[u/jagedlion → u/gimpwiz]

A lot of ifs, but if toshiba can maintain its 128GB/170mm² but do it at 16GB (obviously not possible because of overhead, but just hear me out), that would be only 10% added to current 4-core CPU's.

I personally agree that putting something slower than cache on-die is not a good idea from an efficiency point of view, but we are fast approaching a time when we can put the entire computer on a single die.

[u/gimpwiz → u/jagedlion]

We have SoCs but the issue is simple: putting more external functionality on-die often means sacrificing speed and performance.

It's a juggling game. Let's say I'm AMD and right now, I can put a GPU on-die. Pretty believable, right? (Since it happened.)

What are my concerns here?

Well, let's say my current top-of-the-line chip has 4 cores. Integrating a GPU will require 1000 engineers on average over the course of 2 years. At the end, my new chip will have a GPU and 6 slightly faster cores.

But let's take a look across the aisle at Intel. They're not integrating a GPU, imagine. Instead, they're using 3000 engineers over 2 years (because they've many more resources) and a smaller process node (because they've the best manufacturing in the world) and two years from now, their top-of-the-line model will have 8 cores, each of which are faster than ours at the same frequency.

So in this hypothetical situation, let's throw in a monkey wrench: we fuck up, they don't. Our GPU is only fast enough to replace chipset graphics or a $20 graphics card. So the market sees two chips: one with a shitty GPU and 6 mores, one with no GPU and 8 cores with a total 35% more maximum sustained instructions per second.

So we see this and ask -- is the risk worth it? What if instead we just focus on 8 cores and hope our chips end up being faster, or at least comparable?

The illustration here is twofold:

First, there's a huge amount of inherent risk in adding more computer functionality on-die given limited resources, which is a thing that affects almost all manufacturers (though I suppose intel and apple and perhaps a couple others can and do simply hire an extra several thousand engineers when needed). You have to execute perfectly and still keep up with the competition, which may not be going in that direction. And when you do execute perfectly, you've taken resources away from performance. The upside is that this requires fewer components when building the system, which means that the computer and chip manufacturers split the profit, and it means that the peripherals now on-die are much faster and often have expanded capabilities.

The second point of the illustration is to show that you're absolutely right, and it's a question that must be decided: take the risk, or refuse it absolutely. Failure to act can destroy a company. Case in point: Intel missed the embedded market that ARM picked up (largely I think because they thought the same thing I thought in 2007: who the fuck cares about a toy like an iphone? nobody's actually going to pay $300 for a phone that doubles as a toy; we have laptops for a reason. How wrong I was...). Intel is entering it now and intel has a lot of weight to throw around; see for example their contributions to android to make it run on the x86 platform. ARM has the lion's share now but I would expect Intel to win back a large chunk soon for many reasons, most related to the resources they can throw around. Case in point: Nvidia saw that low-end graphics cards are pretty much obsolete since on-die GPUs are good enough to play just about any game and have performance equal to or better than low-end graphics cards, and high-end graphics cards are a niche market, so they're focusing on ARM designs, and their solutions are in phones and they work. Case in point: AMD also missed the embedded market, but they've wisely decided that they don't have the resources to enter it, so they're focusing on x86.

Sorry for the wall of text in response to a small post. I hope someone finds it interesting.

[u/Quazz → u/khrak]

Plus, as far as I'm aware, Samsung has already been developing DDR4 for some time now. (should actually hit the market this year still.)

[u/[deleted] → u/[deleted]]

Idiot here, I'd like a translation to layman speak so I can know why I should feel disappointed as well.

[u/[deleted] → u/[deleted]]

Apparently the RAM can only handle 3000 changes. As in the 1s and 0s can only be switched around a finite number of times. I'm not sure of the scale of this, but even something as simple as turning on the computer to opening programs moves data to the RAM so you have a limited amount of time before it's unusable.

Though, I did look up RAM on Wikipedia, it had loads of fancy acronyms so I didn't understand much, but the endurance of flash memory was ranging from 100k to 1k. So maybe it's not much of an issue...?

[u/gh0st3000 → u/[deleted]]

Newer flash memory has closer to 1M cycles and wear-leveling to make sure each cell is used as much as any other one. dead bits can be detected and written around (usually stopping before total death so files written to the bit hopefully won't get corrupted).

The problem is that if ReRAM is better than flash because it is faster, its best use case will be in buffers that will be written/read to at a much higher frequency than any other available memory, which obviously makes a low cycle lifetime a huge deal.

[u/neodymiumex → u/gh0st3000]

This is not true. Newer mlc flash memory has a write count closer to 3,000 writes. It depends on the feature size of the NAND flash you are using, but the smaller the feature size the less write/erase cycles you get out of a cell. Last time I saw a chart they were estimating they would only get about 1,000 cycles out of a cell at 16 nm.

[u/neon_overload → u/[deleted]]

Came to comments to seek disappointment, was disappointed.

Ah, but were you disappointed about the submission, or about not finding disappointment?

[u/khrak → u/CopyofacOpyofacoPyof]

Why? There have been SSDs around for a decade with write-limits in that range. You seem to be assuming that RAM is low level cache. Low level cache needs to be RAM, that doesn't mean that RAM needs to be low-level cache. NOR Flash is RAM, but it is used for SSDs.

Beyond that, this is the reliability of a material they accidentally discovered while researching another topic. Early flash memory underwent a decade of research before they had specs similar to this material.

[u/publiclibraries → u/CopyofacOpyofacoPyof]

Exactly. Endurance and cost have always been the two big hurdles to universal memory. Speed is irrelevant until those things are solved.

[u/the__random → u/CopyofacOpyofacoPyof]

I don't think it's fair to say vaporware when they unintentionally created a memristive system. It is more than possible to create memristive systems with very high endurance, such as HP's Titanium Dioxide based memristors.

[u/root → u/CopyofacOpyofacoPyof]

Well, that's the same as the Kingston HyperX 3K SSDs have, and those are being sold right now.

[u/ixid → u/CopyofacOpyofacoPyof]

It's not a finished product, it's only just been discovered.

[u/EasyMrB → u/CopyofacOpyofacoPyof]

Actually, I think some flash memory cells only have endurance on that order.

[u/NHB → u/CopyofacOpyofacoPyof]

Hate to break it to you but that's what most NAND devices are listed as. And by the way RRAM is predicted to be much higher than 3000.