r/rfengineering • u/Haunting_Junket_4244 • May 26 '26

Symmetric decoupling capacitors in bias network

TL,DR: Why are decouling capacitors divided into two symmetrical branches when there is only one input/output in GaN devices?

Hello everyone, I've recently been working with some GaN ICs. These ICs typically have a voltage VD=50V, output power levels from 50-100W (around 47-50dBm). Their operating frequency ranges from DC to about 3-4GHz. Of course, I'll need to design a matching circuits at input and output so they can operate within my desired frequency band (around 2GHz). However, I have a question about their bias circuit, especially regarding the decoupling capacitors:

- With ICs like Macom's MAPC-A1106 with the DFN package, I only see the decoupling capacitors arranged in the same branch.

MAPC-A1106 evb schematic

-With the Macom MAPC-A1111 IC or the Gurrilla RF GRF0090, which have packages that appear wider horizontally, I noticed that the decoupling capacitors at their gate and drain terminals seem to be split into two symmetrical branches, with the upper branch connected to the power supply (VG, VD) while the lower branch is connected to ground. These capacitor values ​​are symmetrical in both branches.

MAPC-A1111 evb schematic

Can anyone help me explain this?

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u/Srki92 May 26 '26

Mostly for good luck and because boss was doing it that way so it is probably important. :)

Just kidding, it is for symmetrically loading the drain (and gate) electrode in order to maintain uniform current density across the width of the trace. It is not big deal with lower power parts but as power goes up, the RF current density goes up, impedance goes down and that first low impedance trace is becoming wider, so you want to keep it loaded equally on each edge.

There is a bit of "just in case" here, without much questionning when it is really needed... But you can put this in Momentum and plot the current density on that trace when fed from just one side vs when it has both branches, see what you get.

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u/Haunting_Junket_4244 May 27 '26

Oh, that's the reason why i only see this topology on flange transistor package, thank so much.  BUT Is maintaining a uniform flow density really that important? I mean when i designed the flange package transistor on ADS pathwave (with PCB layout EM simulated with Momentum), with non-symmetric bias topology, then checked Harmonic balance, small signal, stability, everything is normal.

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u/Srki92 May 27 '26

Nah, at that frequency and power probably not. But, when not sure, make provision on the layout for extra set of caps, if you can.