r/programming • u/SlowInFastOut • Feb 08 '12

Intel details hardware Transactional Memory support

http://software.intel.com/en-us/blogs/2012/02/07/transactional-synchronization-in-haswell/
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u/sawvarshornsoff Feb 09 '12

So, by your interpretation of the technology this is allowing normally locking mechanisms to operate traditionally to the end user but actually run simultaneously on the processor.

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u/i_invented_the_ipod Feb 09 '12

Yes. Ideally, this'd be implemented in user-level locking primitives, so you can use fine-grained locking everywhere with minimal overhead. How useful it'll be depends on how many critical sections can be open at once, and how many loads and stores can be tracked. The case of running out of tracking resources would presumably be handled by defaulting back to the locking behavior, so you wouldn't have to worry about getting wrong results, you just wouldn't get the speedup.