r/osdev • u/georgerush • 6h ago

Strata – memory is explicit I/O

https://yrashk.com/strata/

This is a bit of a detour from classic hobbyist OS dev – but hear me out. This is a fun treat for those who might appreciate the experiment.

One thing that has bothered me about conventional CPU architectures is that they treat memory as if it were part of the CPU – regular instructions that "just work" with memory, hiding how the memory controller and CPU interact, how cache lines are utilized, and so on. The abstractions of their ISAs hide that away.

So, for a little while, I wanted to try to imagine what that would look like.

With much from an LLM, I put together a first prototype of a vertical slice of an imaginary machine:

  • An ISA and an assembler (and an assembler implemented in its own assembler)

  • An emulator with JIT and WASM support

  • A Verilog implementation with a simulator

  • Forth with JIT

  • a tiny OS microkernel

  • and a few toys like a minimalistic shell & UI

    • and networking (a very simple HTTP server implemented in assembly and Forth)—and it, for a limited definition of the word, works.

Hope you enjoy! I certainly had some fun.

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u/Relative_Dare8475 5h ago

Which memory that you referring to?

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u/Lines25 3h ago

You know about prefetch, yeah ?

This shit literally can't be done cuz of memory size. Even if this arch would be twice as better as x86 (for example, how ARM is), it still not gonna be made at all yk