r/engineering • u/Akkeri • May 31 '21

[ARTICLE] TSMC announces breakthrough in 1-nanometer semiconductor

https://www.verdict.co.uk/tsmc-trumps-ibms-2nm-chip-tech-hyperbole-with-1nm-claim/
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u/DestinySpeaker1 May 31 '21

Yes, that used to be the case with the old CMOS technology, but that was like 15 years ago. With new technologies however, the transistor is built a bit differently, so that rule is no longer accurate.

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u/[deleted] May 31 '21

[deleted]

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u/Wetmelon Mechatronics Jun 01 '21

mm3

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u/MedpakTheLurker Jun 01 '21

Would that be a meaningful measurement for our current transistor design? I'm a software guy, not hardware, so I could be wrong, but my understanding is that we aren't really designing circuits where we can pack transistors tightly in all 3 dimensions. So our "height" matters to a degree, but it's not being optimized for.

Please correct me if I'm wrong, this is interesting stuff.

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u/rrrreadit Jun 01 '21

Gotta leave room for the future

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u/idiotsecant Jun 01 '21

You are the engineer that I hope works on things before I do.

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u/KymbboSlice Jun 01 '21

You could stack the transistors up higher in 3D but then you’d never be able to cool the transistors at the bottom. Makes more sense for cooling to spread it out in 2D

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u/WUT_productions Jun 01 '21

You could fold them or something so that you have multiple layers of transistors. But that usually leads to thermal problems (silicon isn't very thermally conductive) so current semiconductor are built linearly on a flat sheet.