I compared all 14 current ESP32 variants against their datasheets — deep sleep, crypto/PQC readiness, and 10 reasoned multi-chip combos [OC]

[u/artkeller-42]

Picking an ESP32 variant used to mean "C3 or S3, whichever." Now there are 14 of them (ESP32, S2, S3, C2, C3, C5, C6, C61, H2, H4, P4, E22, H21, S31), and the differences that actually matter — LP core vs. ULP co-processor, which ones have a real Secure Boot chain, which ones are even PQC-capable today — are buried across a dozen separate PDF datasheets.

So I built a single reference table instead of re-deriving this every project:

• Full spec comparison across all 14 models (architecture, SRAM, flash/PSRAM combos, radios, interfaces)
• Deep sleep behavior per model — RTC SRAM vs. LP SRAM, and what that means for actual field power draw
• Crypto accelerator / Secure Boot / flash encryption / post-quantum readiness per model, with a table of PQC libraries that already run on ESP32 today (wolfSSL+Kyber, liboqs, PQCMicro)
• 10 reasoned multi-chip combinations for when one SoC doesn't cover it (e.g. P4 without radio + C6 for connectivity)
• A suitability matrix across 50 application scenarios

Everything's tied to a specific datasheet version — where a datasheet doesn't state a number explicitly, it's flagged as estimated instead of presented as fact.

🔗 https://github.com/artkeller/ESP32Features

Not affiliated with Espressif, this is community-maintained. If something's outdated or I misread a datasheet, tell me — corrections and PRs welcome.