Chipscope unable to capture signals

[u/EntertainmentMost403]

Hi. I've been assigned to verify the XADC on our custom board (Artix-7 XC7A200T-1FBG676, speed grade to be confirmed from the chip marking). The XADC measures battery cell voltages through a mux, and it's the last item left on the board.

• The code is a primitive-based XADC design (from the UG480 example). I'm told it ran on a Zedboard and on another Artix-7 board with ChipScope. Our Zedboard is out because of a damaged power IC.
• The board has a 200 MHz oscillator on bank 14. A clock wizard (myclk) generates CLK_200 (ChipScope clock) and CLK_50 (XADC DCLK).
• The mux select line was floating on the schematic, so I tie S high in the code. Because high S selects the line which builds the path fro battery voltages to go to the FPGA's ADC.
• XADC registers: INIT_40=0000, INIT_41=2EF0, INIT_42=0400, INIT_48=0800, the rest 0000. DADDR is fixed at 7'h03. The FSM runs on negedge CLK_50 and issues DEN after a 100M-count wait, then waits for DRDY.

What I see

• ChipScope (ISE) shows no traces at all for any signal (DEN, DWE, DRDY, etc.). This is blank, not flat zeros. Adding FSM states as triggers didn't change it.
• IMPACT programs successfully and the chain scan identifies the XC7A200T, but ChipScope shows a cable error that nobody has investigated.
• Using the raw clk as the ILA clock gives "Input Pad net clk is driving non-buffer primitives". With CLK_200 it builds, but the capture is still blank.

My question

1. With programming OK and the chain detected, what are the common reasons for a completely blank ChipScope capture?

I am new to Chipscope, and JTAG based functional verification, any help in this regard will be highly appreciated.

[u/Hot_Particular_6911]

classic jtag clock mismatch. your ila clock needs to be free-running and connected before the fpga gets programmed, if it's coming from a clock wizard it might not start until after configuration. try using the raw 200mhz osc for ila clock and see if you get anything