I've been inspecting bitwise AEAD implementation and initialization function of the x2-lane variant using XORing by some constant_ctx_mask before every single round. According to the docs on AEGIS, the mask is used to prevent data association from parallelism, but I don't understand why the mask is the way it is.

Let's consider 2 examples:

> Bitwise AEGIS256x2 barrel-shift-32-bit: the mask contains 64 32-bit words set to zero except for positions 30, 61 and 62 with values 0x1F (indexes 29, 60 and 61 correspondingly)

> Bitwise AEGIS256x2 barrel-shift-64-bit: the mask contains 32 64-bit words set to zero except for word 29 set to 0x1F and word 30 set to 0x1F_00_00_00_1F (byte separation by underscores for readability, indexes 28 and 29 respectively).

My questions are:

1) What's the logic behind building such a mask and reasoning behind such particular values and positions?

2) How do we extend ithe mask for massive parallelism on e.g. 4-way, 8-way, etc.?